Method and apparatus for multi-thread accumulation buffering...

Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...

Reexamination Certificate

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C712S004000

Reexamination Certificate

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07111156

ABSTRACT:
A method and apparatus for enhancing flexibility of instruction ordering in a multi-thread processing system that performs multiply and accumulate operations is presented. A plurality of accumulation registers is provided for storing the results of an adder, wherein each of the plurality of accumulation registers corresponds to a different thread of the plurality of threads. The contents of each of the plurality of accumulation registers can be selected as an input to the adder such that the present accumulated value can be added to a subsequently calculated produce to generate a new accumulated value.

REFERENCES:
patent: 5278781 (1994-01-01), Aono et al.
patent: 5404469 (1995-04-01), Chung et al.
patent: 5522085 (1996-05-01), Harrison et al.
patent: 5598362 (1997-01-01), Adelman et al.
patent: 5673377 (1997-09-01), Berkaloff
patent: 5896517 (1999-04-01), Wilson
patent: 5909695 (1999-06-01), Wong et al.
patent: 5933627 (1999-08-01), Parady
patent: 6340972 (2002-01-01), Fox
patent: 6343356 (2002-01-01), Pechanek et al.
patent: 6446193 (2002-09-01), Alidina et al.
patent: 6560629 (2003-05-01), Harris
Hamacher, V. Carl; Vranesic, Zvonko G.; and Zaky, Safwat G. “Computer Organization”. Second Edition. New York: McGraw-Hill Book Company © 1984. pp. 8-9.
Byrd, Gregory T. and Holliday, Mark A. “Multithreaded Processor Architectures”. IEEE Spectrum. Aug. 1995. pp. 38-46.
Killeen, Tim and Celenk, Mehmet. “Relocatable Register Sharing Technique for Multithreaded Processor Architectures”. IEEE. © 1994. pp. 545-549.
Eggers, Susan J.; Emer, Joel S.; Levy, Henry M.; Lo, Jack L.; Stamm, Rebecca L.; and Tullsen, Deam M. “Simultaneous Multithreading: A Platform for Next-Generation Processors”. IEEE Micro. © 1997. pp. 12-17.

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