Method and apparatus for multi-port memory controller

Details Method and apparatus for multi-port memory controller Method and apparatus for multi-port memory controller

2006-05-30

2006-05-30

Myers, Paul R. (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Protocol

C710S018000, C711S151000, C711S152000, C370S232000

Reexamination Certificate

active

07054968

ABSTRACT:
A memory controller is provided. The memory controller includes an initiator block configured to arbitrate requests corresponding to data from multiple ports. The initiator block includes an arbitration module configured to consider a latency factor and a bandwidth factor associated with the data from a port to be selected for processing. A state machine is in communication with the arbitration module. The state machine is configured to generate a signal to the arbitration module that is configured to select the data associated with the port based upon the latency factor and the bandwidth factor. Task status and completion circuitry configured to calculate the bandwidth factor based upon previous data selected from the port is included in the initiator block. The task status and completion circuitry is further configured to transmit the calculated bandwidth factor to the state machine. A method for arbitrating across multiple ports is also provided.

REFERENCES:
patent: 5740380 (1998-04-01), LaBerge et al.
patent: 5953685 (1999-09-01), Bogin et al.
patent: 6028841 (2000-02-01), Lyon et al.
patent: 6035360 (2000-03-01), Doidge et al.
patent: 6092186 (2000-07-01), Betker et al.
patent: 6178475 (2001-01-01), O'Brien
patent: 6199127 (2001-03-01), Ajanovic
patent: 6324616 (2001-11-01), Chrysos et al.
patent: 6363445 (2002-03-01), Jeddeloh
patent: 6381649 (2002-04-01), Carlson
patent: 6470238 (2002-10-01), Nizar et al.
patent: 6507530 (2003-01-01), Williams et al.
patent: 6651124 (2003-11-01), McAllister
patent: 6654833 (2003-11-01), LaBerge
patent: 6662278 (2003-12-01), Kahn et al.
patent: 6735653 (2004-05-01), O Mathuna et al.
patent: 6741096 (2004-05-01), Moss
patent: 6742064 (2004-05-01), Waldie et al.
patent: 6772352 (2004-08-01), Williams et al.
patent: 6784890 (2004-08-01), Bergeson et al.
patent: 6799276 (2004-09-01), Belissent
patent: 6820152 (2004-11-01), Kanzaki et al.
patent: 2002/0062415 (2002-05-01), Wang et al.
patent: 2002/0116562 (2002-08-01), Mathuna et al.
patent: 2003/0172213 (2003-09-01), Garcia et al.
patent: 2005/0060452 (2005-03-01), Rengarajan

Affiliated with

Also associated with

Rating

Method and apparatus for multi-port memory controller does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for multi-port memory controller, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for multi-port memory controller will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3582793