Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-09-27
2004-05-25
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S170000, C711S133000
Reexamination Certificate
active
06742083
ABSTRACT:
BACKGROUND
This invention relates generally to the implementation of complex computations in an environment that has limited storage and execution resources. More particularly, this invention relates to processors which are required to execute complex algorithms and which have limited memory, such as random access memory (RAM).
In the audio/video field, complex algorithms must often be performed to decompress and manipulate audio and video data so that the data can be broadcast in real time. For example, use of MPEG protocols to transmit data requires that header information be removed from the payload data before the payload data can be displayed or played. Similarly, where data is compressed, the data must be decompressed so that it can be put to use. In addition data is often manipulated to achieve some sort of effect, such as an enhanced audio or video effect. For example, where a change in color tone or contrast is desired, video data can be changed. Where a change in audio quality is desired, the audio data can be manipulated. Thus, a variety of processes can be performed on audio and video data. Nevertheless, it comes at a cost of time and resources.
When complex algorithms are implemented, they require a great deal of resources. Namely, they often require that a long sequence of instructions be implemented by a computer program, e.g., tens of thousands of different instructions. They also often require a great deal of memory for the storage of operands and data. Hence, when these algorithms are to be implemented by a standalone device such as a microprocessor or a set-top box in which memory for the storage of instructions and memory for the storage of data is limited, it becomes extremely difficult to implement the algorithms.
In addition, it is often necessary to mix and match different algorithms (e.g., MPEG) decoding with Prologic processing or DTS decoding with small speaker adjustments). Furthermore, it is inevitable that additional algorithms will be created in the future which will need to be able to interact with present algorithms. Thus, there is a need for a well-defined way in which the older algorithms can be implemented to interact with future additions.
Thus, there is a need for a device which is capable of allowing complicated mathematical algorithms to be performed while utilizing a limited amount of on-board random access memory by a processor. There is also a need for a system that allows portions of code for an algorithm to be moved into memory of a processor in an organized manner such that the disadvantages outlined above can be overcome. Similarly, there is a need for a system that permits a microprocessor to implement the code for an algorithm that cannot be stored completely by the local memory of the microprocessor in a time efficient manner. Another need is for a system that provides a framework that defines a manner in which algorithms are interchangeable into memory. Similarly, there is a need for a well-defined system in which new algorithms can be implemented with existing algorithms.
SUMMARY
One embodiment of the invention provides a system for processing data by providing a processor; providing a local memory for use by the processor, the local memory having a plurality of memory segments where code or data can be stored; providing a storage location for storing semaphore values, each semaphore value being associated with one of the memory segments and operable to indicate whether the associated memory segment contains code or data available for use; providing a first program operable to access the storage location for storing semaphore values; and providing a second program operable to access the storage location for storing semaphore values. Code operable for implementing the functions of the system allow for the system to be implemented by a processor, such as in a microprocessor based system.
REFERENCES:
patent: 3596257 (1971-07-01), Patel
patent: 3753239 (1973-08-01), Lindsey et al.
patent: 4084224 (1978-04-01), Appell et al.
patent: 4888691 (1989-12-01), George et al.
patent: 4947477 (1990-08-01), Little
patent: 5109499 (1992-04-01), Inagami et al.
patent: 5276847 (1994-01-01), Kohn
patent: 5335325 (1994-08-01), Frank et al.
patent: RE34850 (1995-02-01), Murakami et al.
patent: 5465361 (1995-11-01), Hoenninger, III
patent: 5499348 (1996-03-01), Araki et al.
patent: 5561786 (1996-10-01), Morse
patent: 5579520 (1996-11-01), Bennett
patent: 5765025 (1998-06-01), Morimoto et al.
patent: 5903917 (1999-05-01), Douccur et al.
patent: 5968143 (1999-10-01), Chisholm et al.
patent: 6058474 (2000-05-01), Baltz
patent: 6161169 (2000-12-01), Cheng
patent: 6170049 (2001-01-01), So
patent: 6175900 (2001-01-01), Forin et al.
patent: 6182203 (2001-01-01), Simar, Jr. et al.
patent: 6205522 (2001-03-01), Hudson et al.
patent: 6237065 (2001-05-01), Banerjia et al.
patent: 6240497 (2001-05-01), Yagi
patent: 6292871 (2001-09-01), Fuente
Anderson Matthew D.
Beyer Weaver & Thomas LLP
Genesis Microchip Inc.
Kim Matthew
LandOfFree
Method and apparatus for multi-part processing of program... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for multi-part processing of program..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for multi-part processing of program... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3199641