Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2006-06-27
2006-06-27
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257SE21524, C331S105000, C324S765010, C324S654000
Reexamination Certificate
active
07067842
ABSTRACT:
The present invention includes a method and apparatus for measuring a parasitic inductance associated with a portion of an integrated circuit fabricated on a semiconductor substrate. A test chip for measuring the parasitic inductance is fabricated together with the integrated circuit on the semiconductor substrate. The test chip includes an LC oscillator circuit having at least one substructure that resembles the portion of the integrated circuit and at least one varactor having a capacitance adjustable by a control voltage. When the LC oscillator circuit is connected to the control voltage source and the control voltage is at a certain level, an oscillation is generated in the LC oscillator and the frequency of oscillation can be used to determine the parasitic inductance associated with the portion of the integrated circuit.
REFERENCES:
patent: 6560567 (2003-05-01), Yechuri
Jayapalan Jayakannan
Li Liping
Liu Yow-Juang
Altera Corporation
Flynn Nathan J.
Morgan & Lewis & Bockius, LLP
Wilson Scott R.
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