Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-10-19
2001-09-18
Ray, Gopal C. (Department: 2181)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C713S501000, C710S106000, C324S765010
Reexamination Certificate
active
06292908
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to data processing systems, and more specifically, to methods and apparatuses residing in such systems that allow for the monitoring of signals, that might otherwise be unobservable, at a reduced frequency.
BACKGROUND OF THE INVENTION
The evolution of the computer industry has been driven by the insatiable appetite of the consumer for ever increased speed and functionality. To meet this demand, computer designs rely on, among other innovations, two major techniques: increased frequency of operation for the circuitry comprising the computer system, and increased integration of functions onto a single integrated circuit (referred to as a very large scale integrated circuit, or VLSI chip).
These two techniques are interrelated. By placing more functionality onto a single integrated circuit, a greater frequency of operation for the communication paths between functional units can be achieved. Circuitry interconnect within a VLSI chip is typically one to two orders of magnitude faster than interconnections between physically distinct chips.
Increased density allows more functional units and their communication paths to be integrated onto a single VLSI chip as opposed to multiple chips interconnected by a circuit board, MCM (multi-chip-module), or other means. Communication paths between functional units in an overall design are becoming an increasingly dominant factor in the overall performance of computing systems.
In addition, the progression of chip fabrication technology allows for higher frequency circuits and higher density circuits. This results in more functions being integrated onto a single VLSI chip and the circuits in these higher integration chips operating at ever increasing frequencies.
Increased density and higher frequency provide for increased performance and lower cost to the consumer. However, these design trends produce difficulties for chip designers. As the density of integration of circuits on a typical VLSI chip increases, chips become more complex functionally and therefore more prone to design errors. Prefabrication simulation and verification techniques are used to remove as many design faults as possible. Unfortunately, these techniques fail to produce a chip guaranteed to be free of design errors and, inevitably, debugging of a chip's design occurs after the chip has been fabricated and introduced into a system.
However, once a chip is fabricated, it is often impossible to directly observe the internal communication paths between functional units. These internal paths cannot be directly connected to test equipment to monitor their behavior. Access to these internal communication paths can be critical for debugging errors in a design.
In order to alleviate this problem, a number of chip pins are often dedicated to providing external visibility to one or more on-chip communication paths. The internal communication paths are connected to these dedicated pins which are then further connected to a connector providing an attachment point for test equipment. While this method does allow for monitoring of bus signals, it involves certain limitations.
The frequencies achieved by these on-chip interconnection paths can place an extreme burden on available test equipment. These frequencies can be difficult or impossible to monitor with the commercially available test equipment even though the internal communication path is exposed to the test equipment. Even in those cases where the frequency of operation is within the capabilities of available equipment, higher frequency operation requires the use of more expensive test equipment. Furthermore, as frequencies increase, the amount of functionality available from and number of signals that can be monitored simultaneously by the test equipment decreases.
It would, therefore, be a distinct advantage to have a method and apparatus that would allow for the monitoring, without loss of information, of internal communication paths of a VLSI chip at a lower frequency of operation. The present invention provides such a method and apparatus.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an apparatus and method for monitoring an internal communication path, i.e. an internal bus, of an integrated circuit. The internal bus operates at a particular frequency, f
b
. An image of the internal bus is produced, operating at a lower frequency of operations, f
o
, which is more amenable to monitoring by test equipment.
Signals are received from and driven to the bus using driver/receiver circuitry. The signals may be input-only, output-only, or bi-directional (i.e. input/output) signals. The signals to be monitored, which are typically a subset of the available bus signals, are tapped in the driver/receiver circuitry. Depending on the placement of the signal taps in the driver/receiver logic, the signals may be “out-of-phase” with respect to one another. That is to say, each of the various signals may be coincident with, or delayed or advanced by, one or more cycles relative to the internal bus in time. A buffer/align unit processes the signals in order to produce a time delayed version of the signals. The buffer/align unit is used to bring each of the monitored signals back in phase relative to one another.
Encoding circuitry encodes the time delayed version of the bus in a manner that produces an image of the bus at the lower frequency of operations, f
o
. The encoding circuitry considers the values of the monitored signals over an encoding window, and produces an encoded value for each signal at the lower frequency of operations, f
o
.
Most signals in bus protocols fall into one of three categories. First, the signal value need only be sampled once per operation, and the timing of when the signal is asserted or valid within an encoding window can be derived from other signal(s) in the protocol. Second, the signal can only be asserted once per operation, and the timing of when the signal is asserted within an encoding window cannot be derived from other signals in the protocol. Finally, the signal can be asserted or deasserted for each cycle of an operation, and therefore can take on any value for each cycle of an encoding window. These signals are referred to as Type I, Type II, and Type III signals respectively. The encoding circuitry produces debug signals, referred to as a debug bus, by taking each signal from the buffer/align unit and encoding the signal according to whether the signal is a Type I, Type II, or Type III signal.
REFERENCES:
patent: 5418790 (1995-05-01), Kim
patent: 5784599 (1998-07-01), Elkhoury
patent: 5838692 (1998-11-01), Tobin
patent: 6092132 (2000-07-01), Arimilli et al.
Arimilli Ravi Kumar
Franz Keenan Wynn
Shuler David B.
Williams Derek Edward
International Business Machines - Corporation
Leeuwen Leslie A. Van
Ray Gopal C.
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