Method and apparatus for monitoring illegal conditions in a nonv

Details Method and apparatus for monitoring illegal conditions in a nonv Method and apparatus for monitoring illegal conditions in a nonv

1995-07-28

1996-09-17

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Erase

365195, G11C 700

Patent

active

055575765

ABSTRACT:
A memory chip and method for operating a memory chip, in which one or more nodes are monitored to identify an illegal condition, and a halt signal is asserted in response to the illegal condition. If an illegal condition is identified during a high voltage mode in which high voltage is applied across transistors of the chip, assertion of the halt signal is delayed until the end of the high voltage mode. In response to the halt signal, the chip halts an operation such as a memory cell erase operation. By avoiding halt signal assertion during a high voltage mode, the invention avoids problems (e.g., due to the snap back bipolar effect) which could otherwise result due to switching of transistors of the chip during the process of halting chip operation in the high voltage mode. Preferably, each memory cell of the chip is a nonvolatile memory cell such as a flash memory cell, and the chip includes simple logic circuitry including a flip-flop for generating the halt signal in response to a first signal which indicates that an illegal condition has occurred and a second signal which indicates that the chip is in a low voltage mode.

REFERENCES:
patent: 5355464 (1994-10-01), Fandrich
patent: 5414829 (1995-05-01), Fandrich

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