Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1999-08-18
2001-12-18
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S153000, C711S173000, C711S205000, C711S163000
Reexamination Certificate
active
06332184
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to computer architectures and more particularly to memory access transactions.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a schematic block diagram of a portion of a computer system. As shown, a central processing unit is coupled to cache memory and to a north bridge. The north bridge is coupled to memory, an accelerated graphics port (AGP) bus, and a PCI bus. To access the memory, the central processing unit communicates with the north bridge, which processes all memory accesses. To facilitate such communication, the central processing unit converts virtual addresses or linear addresses (i.e., the address space used by the CPU) into physical addresses.
To make such a conversion, the central processing unit often utilizes page address translations and includes a translation look aside table (TLB) for storing the conversions. Once the conversions are stored, the CPU uses the TLB for subsequent address translations. In general, page address translation utilizes a first part of the linear address to obtain a page directory entry. The page directory entry and a second portion of the linear address are used to obtain a page table entry. The page table entry and a third portion of the linear address are used to obtain the physical address.
The north bridge, upon receiving a physical address from the central processing unit, determines whether the address corresponds to memory, PCI address space, or AGP address space. If the address is directed towards the AGP address space, the north bridge makes a further translation of the received physical address utilizing a GART translation. The translated address is then stored in a GART TLB. If the address is within the PCI address space, the north bridge provides the address on to the PCI bus. If the address is within the memory address space, the address is sent to the memory.
FIG. 2
illustrates a graphical representation of address space within the system of FIG.
1
. As shown, the system virtual (or linear) address space, which corresponds to the central processing unit, has memory spaces for input/output transactions, kernels and processes (i.e., running user applications). The system virtual addresses are converted to physical addresses as previously discussed. The physical address space includes PCI address space, AGP address space, main memory address space and DOS address space. The main memory address space corresponds to DRAM address space, while the PCI address space corresponds to PCI addresses along the PCI bus. The AGP address space corresponds to memory reserved for video graphics processing and the DOS space corresponds to operating system boot-up procedures. For example, the DOS base includes ROM BIOS space, a VGA (video graphics adapter) space, and a RAM space.
As is known, the system of
FIG. 1
processes memory transactions that are targeted for different sections of the physical address space of FIG.
2
. For example, some transactions only involve the memory, others only involve the PCI bus and still others involve both the memory and PCI bus (e.g., read from PCI and write to memory or vice-versa). Further, depending on the mode of operation of the system, the transactions involve different address spaces. For example, when the system is in certain modes of a system memory management (SMM) mode and is processing memory access transactions involving data (e.g., read and/or write data), the transaction utilizes the PCI bus. When the memory access transaction involves instruction codes (e.g., read an instruction code) the memory is utilized. Still further memory access transactions for component emulation (e.g., VGA emulation) access different memory spaces (e.g., the DOS memory space).
In the system of
FIG. 1
, the north bridge determines which memory space will be used for a given transaction. The north bridge makes these determinations on a transaction by transaction basis. Thus, each transaction requires the north bridge to perform processing steps to identify the particular address spaces to be utilized based on the type of transaction and the mode of the system. This occurs even if multiple transactions are accessing the same memory space and the system is in the same mode. As is generally understood in the art, efficiency of a computing system is enhanced by reducing the processing steps required to fulfill a transaction and by reducing redundant operations.
Therefore, a need exists for a method and apparatus that determines the address space or spaces used for like transactions and modes of operation, thereby eliminating the per transaction determination processing and improving a computing system's overall efficiency.
REFERENCES:
patent: 5899994 (1999-05-01), Mohamed et al.
patent: 6157986 (2000-12-01), Witt
ATI International SRL
Song Jasmine
Vedder Price Kaufman & Kammholz
Yoo Do Hyun
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