Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-01-30
2003-02-18
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C700S098000, C700S105000, C700S120000, C700S121000, C430S005000, C378S035000, C382S144000
Reexamination Certificate
active
06523164
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and an apparatus for modifying data of a designed circuit pattern, the data being flattened with losing hierarchical structure.
2. Description of the Related Art
As advance of multi-functionality and high density pattern of semiconductor integrated circuits, the designed data volumes thereof have been increasing, which requires to perform modification of designed pattern data in a shorter time.
FIG. 6
is a schematic block diagram visually showing a cell arrangement included in designed data of a semiconductor integrated circuit.
For example, a semiconductor integrated circuit maker designs subcells C to F in a cell TOP of an entire chip while requesting an outside company to design a subcell A and another outside company to design a subcell B, and arranges the designed subcells A and B into the cell TOP. Generally speaking, CAD data formats of the designed cells TOP, A and B are different from each other, therefore the formats of these cells are converted into a standard format, for example, GDS2 format before incorporating the subcells A and B into the cell TOP. In each cell, names of its subcells are given independently of other cells. For example, the subcell C in the cell TOP and the subcell C in the subcell A are different in contents even though the names thereof are the same.
FIGS.
8
(A) to
8
(C) shows hierarchical structures of the respective subcells A, B and cell TOP of FIG.
6
. Although the hierarchical structures are actually complex, those are simplified for easy explanation.
When the subcells A and B are incorporated into the cell TOP, the subcells A and B are flattened with losing their hierarchical structure since the cell TOP and subcells A and B generally have different formats from each other.
FIG. 7
visually shows a state where the subcells A and B are arranged in the cell TOP.
FIG. 9
shows flattened data (feature data) included in the cell TOP of
FIG. 7
, wherein each subcell includes data of a plurality of features.
In a case where a feature is a rectangle (REC), the feature is represented by coordinates of a diagonal point pair, in a case where a feature is a polygon (POL), the feature is represented by the coordinates of vertex locations and in a case where a feature is a electric line (PTH), the feature is represented by the coordinates of the both ends.
In
FIG. 7
, when modifying a feature in the subcell A, the data of the subcell A are extracted from the file of the cell TOP to make a separate file and an input apparatus is operated while watching a display image to select a feature to be modified and perform modification thereof.
However, in a case where a pattern of 100 contact holes each having the same size is modified, the contact holes have to be modified one by one with manual operation. Assuming that it takes about 10 sec to modify one contact hole, it totally takes about 20 min to modify all of them. This also holds in a similar way in a case where the subcells A and B are extracted from the cell TOP to make a single separate file and a plurality of the same features included therein are modified.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method and an apparatus for modifying flattened pattern data of a designed circuit, capable of modifying the pattern data in a shorter time.
In one aspect of the present invention, there is provided a method for modifying a pattern data of a designed circuit using a computer, the pattern data having a plurality of feature data, comprising the steps of: (a) classifying the plurality of feature data into groups by the computer, each group having feature data of same shapes and same sizes; and (b) when a feature data is selected and modified, automatically modifying other feature data belonging to the same group in the same manner as the selected feature data.
With this configuration, by grouping and automatic modification, the pattern data can be modified in a shorter time.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.
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NN8901248, “Scan Line Algorithm for Layout Compactor of Integrated Cicuits”, IBM Technical Disclosure Bullentin, vol. 31, No. 8, Jan. 1989, pp. 248-251 (6 pages).
Igarashi Shunji
Koike Kazunori
Kik Phallaka
Siek Vuthe
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