Boots – shoes – and leggings
Patent
1988-02-17
1990-05-08
Harkcom, Gary V.
Boots, shoes, and leggings
3647365, G06F 738
Patent
active
049244221
ABSTRACT:
The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.
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Computer Arithmetic, Principles, Architecture, and Design, by Kai Hwang, 1979, pp. 98-101.
IBM Technical Disclosure Bulletin, vol. 25, No. 1, Jun. 1982, Zero Condition Code Detection for Early Resolution of BCS and BCRS, J. J. Losq and G. S. Rao.
Feal Brice J.
Huffman Ann E.
Pechanek Gerald G.
Putrino Michael
Vassiliadis Stamatis
Harkcom Gary V.
International Business Machines - Corporation
Nguyen Long T.
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