Method and apparatus for modeling and circuits with...

Details Method and apparatus for modeling and circuits with... Method and apparatus for modeling and circuits with...

2005-12-06

2005-12-06

Homere, Jean R. (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Timing

C703S013000, C703S014000, C703S015000, C713S401000, C714S033000

Reexamination Certificate

active

06973422

ABSTRACT:
A netlist model of a physical circuit is provided. The netlist model includes a virtual delay element, wherein the virtual delay element is coupled to an asynchronous circuit element.

REFERENCES:
patent: 5649176 (1997-07-01), Selvidge et al.
patent: 5798645 (1998-08-01), Zeiner et al.
patent: 5938785 (1999-08-01), Dargelas
patent: 6295636 (2001-09-01), Dupenloup
patent: 6370493 (2002-04-01), Knapp et al.
Bryant, “Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis”, ICCAD-91, Digest of Technical Papers, 1991 IEEE International Conference on Computer-Aided Design, Nov. 1991, pp. 350-353.

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