Method and apparatus for model-order reduction and...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C703S002000, C703S016000

Reexamination Certificate

active

10839953

ABSTRACT:
Computer time for modeling VLSI interconnection circuits is reduced by using symmetric properties of modified nodal analysis formulation. The modeling uses modified nodal analysis matrices then applies a Krylov subspace matrix to construct a congruence transformation matrix to generate the reduced order model of the VLSI.

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