Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-28
2003-06-24
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C430S030000, C716S030000
Reexamination Certificate
active
06584609
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of electronic semiconductor design and manufacture. In particular the present invention discloses methods for performing optical proximity correction.
BACKGROUND OF THE INVENTION
Semiconductor manufacturers produce semiconductors using optical lithography. Optical lithography is a specialized printing process that puts detailed patterns onto silicon wafers. Semiconductor manufacturers create a “mask” and then shine light through the mask to project a desired pattern onto a silicon wafer that is coated with a very thin layer of photosensitive material called “resist.” The bright parts of the image pattern cause chemical reactions that make the resist material become soluble. After development, the resist forms a stenciled pattern across the wafer surface that accurately matches the desired pattern of the semiconductor circuit. Finally, this pattern is transferred onto the wafer surface via another chemical process.
To improve semiconductor performance, semiconductor researchers and engineers keep shrinking the size of the circuits on semiconductor chips. There are two main reasons to reduce the size of semiconductor circuits: (1) smaller features allow silicon chips to contain more circuit elements and thus be more complex. Similarly, a smaller circuit size allows more copies of the same die to appear on a single silicon wafer. (2) smaller circuit devices use less power and may operate at higher frequencies (faster rates) to produce higher performance semiconductor chips.
As semiconductor circuit sizes have reduced, the limits of optical lithography are being tested. However, the move to new semiconductor processes such as X-ray lithography is viewed as difficult and expensive. To extend the use of optical lithography into feature sizes that are smaller than the light wavelength used in the optical lithography process, a set of sub-wavelength techniques have been developed. Two sub-wavelength technologies that have been developed include phase-shifting and optical proximity correction. Phase shifting utilizes optical interference to improve depth-of-field and resolution in lithography. Optical proximity correction alters the original layout mask to compensate for nonlinear distortions caused by optical diffraction and resist process effects. Optical proximity correction may also correct for mask proximity effects, dry etch effects, and other undesirable effects of the optical lithography process.
Optical proximity correction is often performed by modeling the final manufactured output of a semiconductor design and then determining what changes should be made to the semiconductor layout design to obtain a desired result. The semiconductor process modeling produces very accurate results. However, the semiconductor process modeling is extremely computationally expensive. Furthermore, adjusting a semiconductor layout design using model-based optical proximity correction is a very laborious task. It would be desirable to have a method of using optical proximity correction that produces good results within a short amount of time and reduce human intervention.
SUMMARY OF THE INVENTION
A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.
Other objects, features, and advantages of present invention will be apparent from the company drawings and from the following detailed description.
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Chang Fang-Cheng
Park Hoyong
Pierrat Christophe
Wang Yao-Ting
Zhang You-Ping
Garbowski Leigh M.
Numerical Technologies Inc.
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