Method and apparatus for mirroring units within a processor

Details Method and apparatus for mirroring units within a processor Method and apparatus for mirroring units within a processor

2006-07-25

2006-07-25

Lee, Thomas (Department: 2115)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C713S300000, C713S500000, C714S010000, C714S025000, C714S028000, C714S030000

Reexamination Certificate

active

07082550

ABSTRACT:
A processor responsive to a clock cycle includes a base-unit, a mirror-unit that is a duplicate instance of the base-unit, a non-duplicate-unit in signal communication with the base and mirror units, a first staging register disposed at the input to the mirror-unit for delaying the input signal thereto by at least one clock cycle, and a second staging register disposed at the output of the mirror-unit for delaying the output signal therefrom by at least one clock cycle. The non-duplicate-unit includes a comparator for comparing the output signals of the base and mirror units.

REFERENCES:
patent: 5692121 (1997-11-01), Bozso et al.
patent: 5802359 (1998-09-01), Webb et al.
patent: 6055661 (2000-04-01), Luk
patent: 6498524 (2002-12-01), Kawasaki et al.
patent: 6895540 (2005-05-01), Chen et al.
patent: 2003/0182594 (2003-09-01), Watkins et al.
patent: 2005/0005203 (2005-01-01), Czajkowski

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