Method and apparatus for minimizing weighted networks with...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Reexamination Certificate

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07401303

ABSTRACT:
A method and apparatus are provided for optimizing finite state machines with labeled nodes. Under the method, labels from the nodes are shifted onto the labels of the links connected to the nodes. The finite state machine is then optimized. After optimization, the labels on the links are examined to verify that the prefixes of the labels on each outgoing link match the suffixes of the labels on each incoming link to a particular node. After this verification, a portion of a label on a link is removed from the link and inserted onto the node.

REFERENCES:
patent: 6098034 (2000-08-01), Razin et al.
patent: 6243679 (2001-06-01), Mohri et al.
patent: 2002/0091855 (2002-07-01), Yemini et al.
U.S. Appl. No. 10/620,996, filed Jul. 16, 2003, Office Action dated Feb. 9, 2005 and Amendment dated Feb. 23, 2005.
Mohri, M., “On Some Applications of Finite-State Automata Theory to Natural Language Processing,” Natural Language Engineering, vol. 2, pp. 61-80, 1996.
Mohri, M., “Minimization Algorithms for Sequential Transducers,” Theoretical Computer Science, vol. 234, No. 1-2, pp. 177-201, 2000.

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