Electrical computers and digital processing systems: memory – Address formation – Varying address bit-length or size
Reexamination Certificate
1998-06-18
2001-03-06
Cabeca, John W. (Department: 2752)
Electrical computers and digital processing systems: memory
Address formation
Varying address bit-length or size
C710S120000, C711S172000
Reexamination Certificate
active
06199153
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to computer processor technology, and more particularly to memory subsystems for a multiprocessor system.
BACKGROUND ART
One popular multiprocessor computer architecture is formed by coupling one or more processors to a shared main memory storing data, with each processor typically having a local cache to store its own private copy of a subset of the data from the main memory.
In the above architecture, a separate memory control chip connecting the processors to the main memory manages the operations necessary to access memory from any one of the processors. For example, if one of the processors makes a reference to memory to access data, the control chip will schedule a read of the data corresponding to the reference from the main memory while simultaneously scheduling system probes to the other processors to check for the presence of this address in the other processors' caches.
To connect to the processors of a multiprocessor system, the control chip requires 2*BW*N pins for an N processor system with BW bits for each of two address buses, i.e., the address-out bus for communicating the address of the memory reference from the processor to the control chip, and the address-in bus used by the control chip to send an address of a probe into each of the processors. If BW is large, the control chip can quickly become pin-limited and cannot handle even a reasonable number of processors.
As the size of the multiprocessor system increases, so does the pin count on the memory control chip. Thus, techniques have been proposed which reduce the number of pins located on a processor chip required to connect the processor chip to the control chip, and thereby reduce the total number of pins required on the control chip.
Additionally, with computer processor technology improvements, the total available address space increases, thus typically resulting in more pins on a processor chip to support the larger address bus (i.e., BW increases). It has been observed that many microprocessor systems have limited memory size requirements in that they do not require the maximum addressable memory space provided by the processor architecture. However, even in a multiprocessor system addressing a scaled-down memory space, a microprocessor with a single address bus for all memory size requirements will still require all the address pins be connected to the control chip even though a lesser number of pins are actually needed.
Thus, it is desired to reduce the pin count of the memory control chip for a multiprocessor system with a limited memory size requirement by providing a microprocessor which permits a designer to select an address bus supporting one of a maximum memory size requirement and a small memory size requirement.
SUMMARY DISCLOSURE OF THE INVENTION
The present invention overcomes the foregoing and other problems by providing a computing apparatus having a mode selector configured to select one of a long-bus mode corresponding to a first memory size and a short-bus mode corresponding to a second memory size which is less than the first memory size. Preferably, the first memory size is a maximum memory size and the second memory size is a scaled-down memory size. An address bus of the computing apparatus is configured to transmit an address consisting of address bits defining the first memory size and a subset of the address bits defining the second memory size. The address bus has N communication lines each configured to transmit one of a first number of bits of the address bits defining the first memory size in the long-bus mode. M of the N communication lines are each configured to transmit one of a second number of bits of the address bits defining the second memory size in the short-bus mode. M is less than N. The computing apparatus has N pins, each of the pins respectively attached to a corresponding one of the N communication lines. Thus, the computing apparatus enables a system designer to connect the computing apparatus to a memory controller of a multiprocessor system employing M of the N pins in the short-bus mode, thus reducing the total pincount needed by the memory controller managing a scaled-down memory.
In a further aspect of the present invention an encoder of the computing apparatus provides an encoded packet serving as a vehicle by which an address may be transmitted over a short bus. The encoder arranges the address bits of the address into the encoded packet so that, in short-bus mode, the address bits defining the second memory size are transmitted over the M communications lines of the address bus.
In another aspect of the present invention, the encoder is further configured to map the address bits into an encoded packet forming an array having N rows and C columns, each row and column defining a cell of the packet. Each address bit of the address bits is allocated to at least one of the cells. Preferably, one or more of the cells of the packet includes bits defining command information, and one or more of the other cells of the packet includes bits defining control information. Typically, at least one of the cells of the packet contains a bit indicating a probe miss.
According to another aspect, a time multiplexer of the computing apparatus is configured to transmit the cells of the packet over the address bus in C time cycles. One of the columns of cells is transmitted during one of the C time cycles, the cells in the N rows of the one column being transmitted over the N communication lines in the one time cycle.
In yet another aspect of the present invention, the mode selector of the computing apparatus is further configured to select a third memory size which is less than the first memory size. The address bus of the computing apparatus is further configured to transmit an address consisting of a subset of the address bits defining the third memory size. P of the N communication lines of the address bus are each further configured to transmit one of a third number of bits of the address bits defining the third memory size in the short-bus mode, where P is less than N. Thus, preferably, the computing apparatus may be configured to select one or more memory sizes for the short-bus mode.
In another feature of the invention, the encoded packet is divided into a plurality of parts, each part containing a portion of the address bits arranged so that the address defining the second memory size is transmitted over M of the communication lines. A time multiplexer is configured to transmit the encoded packet defining the second memory size over the M communications lines of the address bus by transmitting one of the parts per a time cycle.
In yet another feature, while in the short-bus mode, an address may be generated to a memory greater than the second memory size because of operating system and other such errors. This memory which is greater than the second memory size, i.e. the addressable memory of the short-bus, is denoted as non-existent memory. A non-existent memory detection unit detects an address referenced to non-existent memory and a handling unit then recovers from this error by canceling the address to non-existent memory and performing other recovery tasks.
In yet another aspect of the method of the present invention, the address bits of the address are partitioned to form a predetermined group of lower-order address bits and a predetermined group of higher-order address bits. The address bits consisting of the concatenation of the lower-order address bits and the higher order address bits define a first address space and the lower-order. address bits define a second address space. The encoded packet is arranged into C columns, each column consisting of N rows, each column and row defining a cell. A portion of the bits of the address are then allocated to cells in each one of the plurality of columns, including mapping the higher-order address bits to the cells of the columns so that rows
1
to M contain the lower-order address bits forming the second address space wherein M is less than N.
Th
Katzman Solomon J.
Keller James B.
Kessler Richard E.
Razdan Rahul
Cabeca John W.
Conley & Rose & Tayon P.C.
Digital Equipment Corporation
Vital Pierre M.
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