Electrical computers and digital data processing systems: input/ – Access arbitrating
Reexamination Certificate
2000-09-19
2004-04-13
Lefkowitz, Sumati (Department: 2189)
Electrical computers and digital data processing systems: input/
Access arbitrating
Reexamination Certificate
active
06721835
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to data transfers in computer systems, and in particular, relates to improving data transfer and bus efficiency by minimizing bus contention when a device reads data from memory.
2. Background Information
In computer systems, components are coupled to each other via one or more busses. A variety of components can be coupled to the bus, thereby providing intercommunication between all of the various components/devices. An example of a bus that is used for data transfer with a processor or for data transfer between a memory and another device is the peripheral component interconnect (PCI) bus.
In order to relieve a processor of the burden of controlling the movement of blocks of data inside of a computer, direct memory access (DMA) transfers are commonly used. With DMA transfers, data can be transferred from one memory location to another memory location, or from a memory location to an input/output (I/O) device (and vice versa), without having to go through the processor. Additional bus efficiency is achieved by allowing some of the devices connected to the PCI bus to be DMA masters.
When transferring data using DMA methods, scatter gather descriptors are often used. High performance I/O controllers, such as gigabit Ethernet media access control (MAC) network controllers, are typically scatter gather descriptor-based bus-mastering devices that allow a computer to communicate with a network. The scatter gather descriptors are used to provide address and control information about data buffers (or “scatter gather elements”) in memory that the controller needs to read or write for I/O operations. For example, the descriptors provide information such as the memory location from where bytes of data are to be moved, the address to where the bytes should go, the number of bytes to move, etc.
To read a data buffer of a memory using DMA transfers, such as when the data has to be retrieved from memory so that the data can be transmitted by the controller, a driver for the controller first prepares the data buffer. This preparation includes querying the data buffer to obtain the data buffer's physical address and length. This information and other control information are then placed by the driver into the descriptor(s). Next, the driver writes to a command register of the controller to inform the controller that the descriptor(s) are ready to be processed. The controller then DMA transfers the descriptor(s) from memory to a first-in-first-out (FIFO) buffer, for example, so that the controller can obtain the data buffer's information (e.g., identify the data buffer's memory location, length, etc.). After the controller has processed the descriptor(s) to obtain this information, the controller can, DMA transfer the contents/data (e.g., frames) in the data buffer referred to by the descriptor(s).
When the driver is given several frames to be transmitted in rapid succession, the writes to the command register to inform the controller of subsequent frame(s) can interfere with data that is currently being read (e.g., currently being DMA-transferred) for previous frames. For example, if the driver is given two frames to send, the driver initially prepares the first frame and writes to the controller's command register to inform the controller that the first frame is ready. Subsequently, the driver prepares the second frame and again writes to the controller's command register to inform the controller that the second frame is ready.
However, this second write to the command register may occur while the controller is attempting to read the data for the first frame. On many computer systems, such writes to the command register are generally slave accesses to the controller that are driven by a bridge. That is, the bridge must remove control of the bus from the controller each time the driver performs the write(s) to the command register. After the write occurs, the controller arbitrates again for control of the bus in order to resume reading the data of a frame. Thus, in the above-described example, the process of informing the controller about the second frame interfered with the reading of the data for the first frame.
In this example and in situations where protocols allow several frames of data to be available at once, the driver is often given multiple frames to send in rapid succession. The bus, contention associated with informing the controller of the frames and the resulting re-arbitration for the bus by the controller reduce the controller's bus efficiency and can cause performance penalties.
REFERENCES:
patent: 5694613 (1997-12-01), Suzuki
patent: 5797041 (1998-08-01), Yasue et al.
patent: 5854908 (1998-12-01), Ogilvie et al.
patent: 5923852 (1999-07-01), Lee et al.
patent: 6094700 (2000-07-01), Deschepper et al.
patent: 6173349 (2001-01-01), Qureshi et al.
patent: 6336157 (2002-01-01), Carbonaro et al.
patent: 6463498 (2002-10-01), Wakeley et al.
patent: 2002/0009075 (2002-01-01), Fesas
Huynh Kim T.
Lefkowitz Sumati
LandOfFree
Method and apparatus for minimizing bus contention for I/O... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for minimizing bus contention for I/O..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for minimizing bus contention for I/O... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3244646