Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-02-14
2004-05-04
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C714S006130, C365S200000
Reexamination Certificate
active
06732229
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to semiconductor memories. In particular, the present invention relates to the implementation of column redundancy for semiconductor memories, whereby defective columns of a memory array are replaced with redundant columns.
DISCUSSION OF RELATED ART
A semiconductor memory typically includes redundant circuitry to increase the functional yield. In general, the redundant circuitry can be classified as row redundant circuitry or column redundant circuitry. Row redundant circuitry includes one or more redundant rows of memory cells and the associated circuitry required to activate the redundant rows and de-activate defective rows of memory cells. Similarly, column redundant circuitry includes one or multiple redundant columns of memory cells and the associated circuitry required to activate the redundant columns and de-activate defective columns of memory cells.
Most conventional column redundancy schemes use one or more dedicated redundant blocks, which can be used to repair any defective blocks. Each redundant block is coupled in parallel with the normal blocks by a programmable element, such as a fuse or anti-fuse. The programmable elements are used to selectively connect the read and write data terminals to a normal block or a redundant block. Each redundant block is capable of being connected to the read and write data terminals associated with any one of the normal blocks. Because each redundant block must be capable of connection to every normal block, long routing paths exist between the redundant blocks and the normal blocks. The long routing paths can create speed critical paths for the memory. Such a column redundancy scheme is illustrated in FIG.
1
.
FIG. 1
is a schematic diagram of a memory circuit
100
that implements a conventional redundancy scheme. Memory circuit
100
includes a memory cell array
101
having a plurality of rows and columns. Memory cell array
101
is subdivided into 130 memory blocks MB
129
-MB
0
. Each of the memory blocks MB
129
-MB
0
includes 8 columns and 1024 rows of memory cells. If memory blocks MB
127
-MB
0
are not defective, these memory blocks are accessed during the normal operation of memory circuit
100
. Memory blocks MB
129
and MB
128
are redundant memory blocks that are used to replace up to two defective memory blocks.
Each of memory blocks MB
129
-M
0
is coupled to a corresponding 8-to-1 column decoder CD
129
-CD
0
. Each of column decoders CD
129
-CD
0
is coupled to a corresponding data line D
129
-D
0
. Data lines D
129
-D
0
normally carry data signals D[
129
:
0
], respectively. Each of column decoders CD
129
-CD
0
is controlled to couple one of the eight columns in its corresponding memory block to its corresponding data line. For example, column decoder CD
3
couples one of the eight columns of memory block MB
3
to data line D
3
.
Each of data lines D
127
-D
0
includes a fuse that can be blown if the associated memory block or column decoder is defective. For example, data line D
3
includes fuse
103
.
Column decoders CD
129
and CD
128
are coupled to redundant data lines D
129
and D
128
, respectively. These redundant data lines D
129
and D
128
extend the width of the memory circuit
100
, traversing data lines D
127
-D
0
. An anti-fuse is provided between each of redundant data lines D
129
-D
128
and each of the normal data lines D
127
-D
0
. For example, anti-fuse
104
is coupled between redundant data line D
128
and data line D
3
. Similarly, anti-fuse
105
is coupled between redundant data line D
129
and data line D
3
.
If all of memory blocks MB
127
-MB
0
and column decoders CD
127
-CD
0
are free of defects, then none of the fuses or anti-fuses are blown. As a result, column decoders CD
127
-CD
0
are coupled to data lines D
127
-D
0
, respectively. However, if one of memory blocks MB
127
-MB
0
or column decoders CD
127
-CD
0
is defective, then the fuse associated with the defective memory block/column decoder is blown, thereby de-coupling the defective memory block/column decoder from its associated data line. An associated anti-fuse is then blown to couple the isolated data line to one of the redundant data lines.
For example, if memory block MB
3
is defective, then fuse
103
is blown to de-couple memory block M
3
and column decoder CD
3
from data line D
3
. Anti-fuse
104
is then blown, thereby coupling data line D
3
to redundant data line D
128
. Under these conditions, redundant memory block MB
128
and redundant column decoder CD
128
provide service to data line D
3
. Redundant memory block MB
129
and redundant column decoder CD
129
can replace a second defective memory block/column decoder in a similar manner.
When redundant data lines D
129
and D
128
are used to route data values, relatively long interconnection delays can exist because of the length of these redundant data lines. In the example described above, the path from data line D
3
to column decoder CD
128
is much longer than any of the other data paths. This interconnection delay becomes intolerable as the ratio of the number of normal columns to the number of redundant columns increases, especially in embedded memory design. The long interconnection delay can create a critical path that effectively increases the access time of memory circuit
100
.
It would therefore be desirable to have a memory system that provides redundancy without adding excessive interconnection delays.
SUMMARY
Accordingly, the present invention provides a memory redundancy scheme for re-routing the data signal paths to disconnect defective memory blocks within a memory array. To implement the redundancy scheme, each of the memory blocks is provided with a corresponding routing control unit. Each of the routing control units includes a fuse which is blown if the corresponding memory block is defective. The routing control units are connected in a chain. A code signal having predetermined default value is provided to a routing control unit at the end of the chain. The code signal is routed along the chain through the routing control units. The code signal is passed through each routing control unit unchanged, unless the routing control unit has a blown fuse. In this case, the routing control unit modifies the code signal. The modified code signal is then passed to the next routing control unit in the chain. In this manner, each routing control unit receives information for all the previous fuses in the chain, adds its own fuse information, and then passes a representative code signal to the next routing control unit. Each routing control unit selects a data signal path in response to its received code signal and the state of its fuse. If the code signal indicates the presence of a defective memory block, the data signal path is modified such that data signals are re-routed to the next or previous memory blocks, depending on the memory array function (read or write). Thus, logically, a defective memory block is disconnected from the original data signal path and replaced by a neighboring memory block. Because each data signal path is only re-routed at most by one (or two) memory blocks, the delays on the various data signal paths are substantially identical. Moreover, the access time with the redundancy scheme is approximately the same as the access time of a memory system without a redundancy scheme. In addition, the above-described process only needs to be performed once after power-on reset. As a result, the normal operation of the memory array will not be affected by the redundancy scheme.
In another embodiment of the present invention, a memory redundancy scheme is provided for re-routing data signal paths to disconnect defective memory blocks in a memory array. Each memory block is provided with a corresponding routing unit. Each routing unit is coupled to its corresponding memory block and at least one additional adjacent memory block. The routing units are configured to route data between functional memory blocks and a data bus. The routing units are controlled by c
Leung Wingyu
Tang Jui-Pin
Bataille Pierre-Michel
Bever Hoffman & Harms LLP
Hoffman E. Eric
Monolithic System Technology, Inc.
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