Method and apparatus for memory optimization in MPE-FEC system

Details Method and apparatus for memory optimization in MPE-FEC system Method and apparatus for memory optimization in MPE-FEC system

2007-01-16

2008-11-11

Chase, Shelly A (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07451378

ABSTRACT:
Systems and methods are provided for processing Multi-Protocol Encapsulation (MPE) under the DVB-H standard. The system includes: (a) a receive buffer having entries organized as columns and rows, the addresses for the entries in the receive buffer being arranged sequentially in column-major order; (b) a first process writing MPE data into the receive buffer, in the manner such that, for each frame, the application data portion and the error correction code portion are written sequentially in column major order, (c) a second process decoding the error correction code portion of each frame and which corrects the application data portion in accordance with the decoding; and (d) a third process reading out the application data portion from the receiver buffer column by column, the third process re-reading any column of the application portion that is corrected by the second process, when that column has previously been read by the third process.

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