Method and apparatus for memory block initialization

Details Method and apparatus for memory block initialization Method and apparatus for memory block initialization

2007-05-22

2007-05-22

Le, Don (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S105000, C365S189020

Reexamination Certificate

active

11048831

ABSTRACT:
In one aspect of the invention, a circuit for generating addresses for memory initialization within a programmable logic device (PLD) is provided. The circuit includes input registers, which are loaded and unloaded with data triggered by the edge of a clock. The circuit further includes multiplexers, where the multiplexers are capable of receiving output of the input registers and encoded programmable addresses. The multiplexer generates encoded row addresses for a wordline of a memory within the PLD. The circuit includes a decoder to decode the encoded row addresses for the wordline of the memory.

REFERENCES:
patent: 6028445 (2000-02-01), Lawman
patent: 6765408 (2004-07-01), Cheng et al.
patent: 6856173 (2005-02-01), Chun
patent: 6924670 (2005-08-01), Azam
patent: 2005/0166105 (2005-07-01), Warren

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