Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1997-07-01
1999-08-10
Canney, Vincent P.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
G06F 1100
Patent
active
059352639
ABSTRACT:
A memory device includes an output data path that transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern. If the data does not match the desired pattern, the comparing circuit outputs an error signal that is input to the output buffer. When the output buffer receives the error signal, the output buffer is disabled and outputs a tri-state condition on a data bus. Since the error signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.
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Fister Wallace E.
Keeth Brent
Lee Terry R.
Manning Troy A.
Martin Chris G.
Canney Vincent P.
Micro)n Technology, Inc.
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