Method and apparatus for memory addressing

Details Method and apparatus for memory addressing Method and apparatus for memory addressing

1999-11-02

2001-11-06

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

C711S129000, C711S163000, C711S202000, C711S211000

Reexamination Certificate

active

06314490

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to addressing memory and more particularly to addressing memory in a processing system that includes a cache.
BACKGROUND OF THE INVENTION
Cache memory is often included in processing systems in order to increase memory accessing efficiency and speed. As is known, cache structures are often limited in size and therefore multiple memory addresses within the memory addressing space are mapped to the same address within the cache structure. Set associative caches are sometimes known to include multiple ways, or sets, that are used to cache different sets of memory locations. For example, the four way cache illustrated in
FIG. 1
includes four separate sets. Each of the sets may be used to cache a different portion of the memory addressing space.
In some applications, different elements being processed may be characterized by a number of parameters. It may be efficient to treat each of these sets of parametric data as stream data, where stream data is accessed with unique memory instructions such that the stream data accesses are distinguishable from normal memory accesses. In one example, primitives in a video graphics processing system are characterized by a number of parameters including color, vertex coordinates, and possibly texture mapping information. Each of these different types of parametric data is stored as stream data and is accessed through stream data memory commands.
Because of the way stream data is accessed, prior art systems often allocated a particular set, or way, within a caching structure to stream data. A stream set illustrated in
FIG. 1
may be such a set utilized for caching stream data. Allocating a particular set to stream data helps to ensure that stream data does not interfere with the caching of other types of data within the cache, which may result in inefficient cache usage.
Although the caching structure illustrated in
FIG. 1
may perform adequately in applications where a single stream is supported, if multiple streams are supported in a system cache, cache “thrashing” may result as the different streams replace each other in the cache. When cache thrashing occurs, cached data is replaced before it can be effectively utilized by the processing system. Data stored in the cache is typically fetched in blocks, and such block fetching of stream data increases the likelihood of cached data being prematurely overwritten. Cache thrashing greatly reduces the benefits of including a cache in the system and can have a detrimental effect on overall system performance.
Therefore, a need exists for a method and apparatus for supporting multiple streams in a processing system that includes a cache structure.


REFERENCES:
patent: 5694567 (1997-12-01), Bourekas et al.
patent: 6128718 (2000-10-01), Schmisseur et al.

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