Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-07-28
2001-09-25
Phan, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06295630
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to: a method and an apparatus each capable of precisely measuring a so-called overlap length of a MISFET (i.e., Metal Insulator Semiconductor Field Effect Transistor), wherein the overlap length forms one of important physical device parameters required in carrying out a circuit simulation of the MISFET such as MOS (i.e., Metal Oxide Semiconductor) transistors and the like; and, further to a recording medium and a device model each carrying an extraction program for determining the overlap length.
2. Description of the Related Art
In the technical field of LSI memories, it takes much time and money to develop a real-world prototype circuit for a new MOS memory, or for realizing a change in a fabrication process such as diffusion processes and like processes of a conventional MOS memory each time such new MOS memory is designed and developed, or such change in the production process is carried out. Consequently, heretofore, in place of such building of the real-world prototype circuit of the new MOS memory in design and development, it has been performed a series of computer simulations in design and development of the new MOS memory.
Such series of the computer simulations comprise: a process simulation for extracting various process data such as impurity concentrations and like process data; a device simulation for extracting various device parameters such as an effective channel length (Leff) and the like on the basis of the process data obtained through the above process simulation; and, a circuit simulation in which an exact value of a drain current (Id) is determined on the basis of the device parametrers obtained through the above device simulation, and a circuit analysis program called “SPICE” (i.e., Simulation Program with Integrated Circuit Emphasis) works so that memory operations, flip flop operations and like operations are investigated.
The more the results of these simulations approarch the results of experiments, the less period of time a desired MOS memory requires in its development. Consequently, demand for precise simulation techniques is very high.
Now, this type of computer simulation will be described in detail.
When a circuit simulation is performed in memory operation or in flip flop operation with respect to a MOS memory newly designed or changed in its fabrication process, it is necessary to precisely extract the device parameters by previously conducting both the above-mentioned process simulations and the device simulations in order that the device model having been incorporated in the circuit simulation may reproduce the actual device characteristics. A conventional method for extracting the device parameters will be now described.
FIG. 10
shows a circuit diagram equivalent to the arrangement of a MOS transistor. A device model of such a MOS ransistor is represented by the following equation (1) in which drain current (Id) is defined.
Id=f
(
p
1
,
p
2
, . . . ,
pN, Vd, Vg, Vb
) (1)
where (p
1
, p
2
, . . . , pN) is a set of the device parameters; Vd is a drain voltage; Vg is a gate voltage; and, Vb is a substrate voltage.
In general, the device parameters have physical quantities, for example such as: an effective channel length (Leff), gate length (L), channel width (W), threshold voltage (Vth), resistance (r
0
) of a diffusion layer (shown in FIG.
10
); an effective mobility (&mgr;e) of movable carriers depending on the gate voltage (Vg); and, the like. Of these parameters, the device dimensions such as the gate length (L), channel width (W) and like dimensions capable of being directly measured are previously determined, and, therefore previously removed from a group of unknown parameters being extracted. On the other hand, assuming that the characteristics of the actually measured device are represented by the following equation (2), extraction of general device parameters is defined as follows: namely, over the entire range of applied voltages which the equation (2) directs, device parameters (p
1
, p
2
, . . . , pN) are selected in a manner such that the characteristics of the device model coincide with those of the actually measured device.
Id=g
(
Vd, Vg, Vb
) (2)
More specifically, when the values of the above two equations (1) and (2) each at the i-th one of M pieces of applied voltages used in measurement are defined to be fi and gi, respectively, the above device parameters (p
1
, p
2
, . . . , pN) are selected so as to make the squared error E=&Sgr;(fi−gi)
2
minimum. In this derivation, generally a so-called “method of iteration” is used with the use of the above-mentioned “SPICE”. In this “method of iteration”: at first, trial initial values of the device parameters (p
1
, p
2
, . . . , pN) are provided; and, thereafter, these device parameters (p
1
, p
2
, . . . , pN) starting therefrom are repeatedly rewritten until their variations assume very small values.
However, when this “method of iteration” is merely applied to the device parameters (p
1
, p
2
, . . . , pN), the thus extracted values tend to become abnormal from a physical point of view in spite of their inherent physical quantities. This is because: irrespective of the fact that the device model represented by the equation (1) does not completely coincide with the actual device in characteristics, a large number of the device parameters are forcibly determined on the basis of delicate differences between the equation (1) and the measured values.
When the device model is defined by the device parameters which are nonsense from a physical point of view, the characteristics of the device model when these device parameters are varied differ from those of the actual device. Particularly, with respect to the dependency of the characteristics on the gate length, the device model differs from the actual device, which poses a serious problem. In other words, as for the device parameters extracted from the device having the gate length L
1
, when the device has its gate length L
1
replaced with another value L
2
, the characteristics of this device differ from those of an actual device having the gate length L
2
.
In order to cover the above deficiency, as for the device parameters which are important from a physical point of view, it is often performed to separately determine these important device parameters before the “method of iteration” is applied to the device parameters. As one of these importance device parameters, it is possible to enumerate the overlap length (&Dgr;L). Here, definition of the overlap length (&Dgr;L) is made as shown in FIG.
11
. More specifically, through the overlap length (&Dgr;L) a gate electrode
81
overlaps both a source diffusion layer
82
and a drain diffusion layer
83
.
Incidentally, as shown in
FIG. 11
, the effective channel length (Leff) is equal to a distance between a source-side p-n junction and a drain-side p-n junction located in the surface of a silicon substrate
84
. In other words, the effective channel length (Leff) is equal to a difference between the gate length (L) and the overlap length (&Dgr;L). Consequently, when the overlap length (&Dgr;L) is determined, it is possible to determine the effective channel length (Leff=L−&Dgr;L).
Heretofore, for example, as disclosed in Japanese Patent Laid-Open Nos. Sho54-2667 and Hei07-176740, derivation of the overlap length (&Dgr;L) has been made by measuring a channel resistance (i.e., a resistance between a source electrode and a drain electrode) R represented by the following equation (4) at each of various effective gate voltages Vge represented by the following equation (3) in each of a plurality of MOS transistors varying in gate length when a drain voltage Vd is very small:
Vge=Vg−Vth
(3)
where Vg is a gate voltage (i.e., a between gate/source voltage); and, Vth is a threshold voltage (i.e., a critical value of the gate voltage between an ON and an OFF mode of the MOS transistor).
R
=(&Dgr;
Id/&Dgr;V
NEC Corporation
Phan Trong
Young & Thompson
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