Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-12-02
2001-10-02
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06298464
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to maximum likelihood sequence detection and more particularly to maximum likelihood sequence detection in a Viterbi decoder.
BACKGROUND OF THE INVENTION
Viterbi decoders are well understood in the art. Such decoders function to reliably recover a data stream of symbols, which symbols can represent one or more bits of information. Viterbi decoders typically function to mathematically manipulate state and branch metrics in order to recover the most likely original symbols. Also typically, each iteration in the Viterbi calculation process will involve a number of addition steps, comparison steps, and selections steps, which addition, comparison, and selections steps are accomplished in a sequential process.
Fast Viterbi decoders typically comprise dedicated hardware platforms, as versus agile software programmable platforms, as the iterative Viterbi calculations can typically be effected more rapidly, at a reasonable cost, in a dedicated hardware platform. Because of the sequential nature of the addition, comparison, and selection steps, hardware solutions, while fast, are not always fast enough to suit all present needs with respect to speed of calculations.
BRIEF SUMMARY OF THE INVENTION
The present invention therefore seeks to provide a faster Viterbi decoder.
Accordingly, in one aspect the invention provides a method of maximum likelihood sequence detection comprising the steps of, during a single symbol period: combining a branch metric with each of a predetermined number of preselected path metrics to produce a corresponding number of resultant path metrics; comparing the predetermined number of preselected path metrics to identify one of the corresponding number of resultant path metrics; and selecting the one of the corresponding number of resultant path metrics.
In another aspect the invention provides a maximum likelihood sequence detector comprising: a first adder having an input coupled to receive a branch metric, another input coupled to receive a first path metric, and an output; a second adder having an input coupled to receive the branch metric, another input coupled to receive a second path metric, which second path metric is different from the first path metric, and an output; a comparator having a first input coupled to receive the first path metric, a second input coupled to receive the second path metric, and an output; and a multiplexor having data inputs coupled to the outputs of the first and second adder, a control input coupled to the output of the comparator, and an output.
REFERENCES:
patent: 4614933 (1986-09-01), Yamashita et al.
patent: 5430744 (1995-07-01), Fettweis et al.
patent: 5815515 (1998-09-01), Dabiri
patent: 5987638 (1999-11-01), Yu et al.
patent: 6070263 (2000-05-01), Tsui et al.
patent: 6148431 (2000-11-01), Lee et al.
Tong Mui-Chwee
Weiner Nicholas
Baker Stephen M.
Motorola Inc.
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