Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
2001-09-28
2004-09-07
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C712S005000, C365S238500
Reexamination Certificate
active
06789180
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing memories generally and, more particularly, to a method and/or architecture for externally reading, on an address bus, the content of either the internal address provided by an address counter/register or a mask register.
BACKGROUND OF THE INVENTION
Typical circuits for reading an address counter/register and matching bus widths through synchronous ports have drawbacks. Such circuits allow the readback of solely the address counter/register, while placing the internal address bits on an external data bus. Typical circuits use complex I/O routing and tristate control logic to allow the readback operation to take place on the I/O data bus. Typical circuits also require loading of the data bus with arbitration/demultiplexing circuits in order to externally extract the address information during a readback operation.
In the case of a larger address bus size, compared with the size of the data bus, the readback operation requires two clock cycles to present the internal address bits to the external data lines. Since the circuit performs the readback operation on the data I/O bus, the effect is reduced data bus speed due to multiple-loaded buses on the data ports. The circuit also requires complex readback control to allow suitable matching between the size of the address and I/O bus, either by tristating the I/O lines not needed in readback mode or implementing a state machine when a size of the readback address is larger than the external I/O bus.
When the address bus size exceeds the I/O bus size, the typical circuit requires one additional clock cycle, slowing down the system. For example, in a multi-port 1 Meg SRAM, internally configured as a x36 memory (i.e., long word format), there are (i) 15 bits readback if bus-matching is not active (i.e., having a x36 I/O bus), (ii) 16 bits readback if bus-matching with an external I/O format of x18 (i.e., a word) and/or (iii) 17 bits readback in two clock cycles if bus-matching with an external I/O format of x9 (i.e., a byte) is configured through the bus-matching specific controls.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a memory device and one or more control circuits. The memory device may be configured to store and retrieve data. The one or more control circuits may be configured to control access to the memory device. Each of the control circuits may be configured to provide a readback of an internal address value when in a first state and a readback of a mask value when in a second state.
The objects, features and advantages of the present invention include providing a method and/or architecture for externally reading, on an address bus, the content of either an internal address provided by an address counter/register when in a first state or a mask register when in a second state that may (i) avoid additional loading of data lines such that external devices may capture mask or internal counter address information at improved speeds, (ii) allow a system designer to make use of single loaded buses on any data port, (iii) maximize data bus speed, (iv) improve overall system speed, (v) provide reduced complexity of readback control devices, (vi) present readback mask/counter bits to the address bus during a single clock cycle, independently of the relative size of the address and I/O buses, (vii) eliminate (or reduce) the need for arbitration/multiplexing schemes on the data I/O bus, and/or (viii) maneuver I/O address related items on the address bus.
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Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Moazzami Nasser
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