Method and apparatus for mapping signals of a device under...

Details Method and apparatus for mapping signals of a device under... Method and apparatus for mapping signals of a device under...

2007-05-29

2007-05-29

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S037000, C714S039000

Reexamination Certificate

active

10430242

ABSTRACT:
A method of mapping device pins to logic analyzer channels in preparation for a digital test includes accepting a correlation of at least one test connector to one or more logic analyzer pods and presenting a display showing available test connector pins for each defined test connector. A user may then select a one to one assignment of one or more signal pins to the test connector pins to establish a mapping configuration.

REFERENCES:
patent: 6396517 (2002-05-01), Beck et al.
patent: 6407736 (2002-06-01), Sontag et al.
patent: 6742143 (2004-05-01), Kaler et al.
patent: 6760866 (2004-07-01), Swoboda et al.
Doug Beck, “Understanding Logic A nalyzer Triggering”, Insight vol. 4, Issue 3 pp. 22-26, 1999.
U.S. Appl. No. 09/432,840.

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