Method and apparatus for mapping memory addresses to...

Details Method and apparatus for mapping memory addresses to... Method and apparatus for mapping memory addresses to...

2006-05-23

2006-05-23

Kim, Hong Chong (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

C711S118000

Reexamination Certificate

active

07051184

ABSTRACT:
One embodiment of the present invention provides a system for mapping memory addresses to cache entries. The system operates by first receiving a memory request at the cache memory, wherein the memory request includes a memory address. The system then partitions the memory address into a set of word offset bits and a set of higher-order bits. Next, the system maps the memory address to a cache entry by computing a modulo operation on the higher-order bits with respect to an integer and using the result as the cache index.

REFERENCES:
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patent: 5649143 (1997-07-01), Parady
patent: 6738890 (2004-05-01), Ishikawa et al.
patent: 2003/0188124 (2003-10-01), Luick
patent: 1 227 405 (2002-07-01), None
“Introducing a New Cache Design into Vector Computers” by Qing Yang, IEEE Transactions on Computers, Dec., 1993, No. 12, New York, pp. 1411-1434, XP 000417776.

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