Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2000-12-08
2004-06-08
Ellis, Kevin L. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
Reexamination Certificate
active
06748512
ABSTRACT:
FIELD OF THE INVENTION
The present disclosure pertains to the field of computer system integration. More particularly, the present disclosure pertains to the field of using system memory for the allocation of a device address range of a programmable device.
BACKGROUND
In order to satisfy the conflicting design constraints of driving cost and power lower while continuing to increase performance in today's computer systems, designers have relied on a number of different methods, including the integration of discrete system components into a core-logic chipset and/or microprocessor.
Device integration has been largely limited to the area of Accelerated Graphics Port (AGP) graphics. Computer systems are available today containing core-logic chipsets containing integrated AGP graphics devices designed to operate at lower power, lower cost, and higher performance than some computer systems containing discrete AGP graphics devices. Moreover, recent advancements in computer system component integration has spawned the integration of AGP graphics within a microprocessor.
In order to continue to lower cost and power, while continuing to increase performance, both approaches rely on system memory for at least some of the integrated device's memory needs. In the area of AGP graphics, for example, system cost and power consumption are driven lower by using system memory for storage of command, data, and texture maps and alleviating the need for costly, power-consuming local graphics memory. In order for the graphics device to map at least a portion of its device memory range to system memory, the graphics driver must request an allocation of system memory from the host operating system. Due to the non-contiguous manner in which the operating system may allocate the requested device memory within system memory, it is further necessary to create a table or ‘map’ that translates linear addresses originating from the graphics device to the actual physical address locations allocated within system memory by the operating system. This is accomplished in the area of integrated AGP graphics through a Graphics Address Re-mapping Translation Table (GART).
Previous methods of re-mapping integrated device address space to system memory have been limited in the number devices that may share an address re-mapping table. Furthermore, these methods are limited in the types of devices that may re-map device address space to system memory. For example, GART may only be accessed by AGP devices.
These limitations severely reduce the number of devices and the device types that may be integrated within a chipset or microprocessor without resorting to external memory solutions. Therefore, cost and power advantages associated with integrating non-AGP devices within a chipset or microprocessor may not be fully realized.
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Buch Deep
Gamsaragan Edward
George Varghese
Pentkovski Vladimir
Zagacki Paul
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