Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-11-27
2000-09-19
Sheikh, Ayaz R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395877, 711149, 711167, 711168, G06F 1300
Patent
active
061224448
ABSTRACT:
A method and apparatus for performing signal processing using incongruent buffers. According to one method described, a maximum concurrent run length (MCRL) is calculated to indicate the maximum run length before any of a plurality of buffers is exhausted. Processing data for each of the plurality of incongruent buffers is then repeated until the maximum concurrent run length has been reached. The calculation of the MCRL may be a determination of which of the plurality of buffers has a lowest remaining time before buffer exhaustion or the least number of remaining buffer entries. A system described includes a processor coupled to memory. The memory contains a plurality of buffer counters and a plurality of memory blocks defining a plurality of incongruent buffers. The memory also contains a MCRL calculation routine for determining the MCRL count from the buffer counters. A data processing routine repeats manipulations of data in the incongruent buffers until the MCRL count is reached.
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Kidder Jeffrey
Shen Albert
Dharia Rupal
Draeger Jeffrey
Intel Corporation
Sheikh Ayaz R.
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