Method and apparatus for managing write-to-read turnarounds...

Details Method and apparatus for managing write-to-read turnarounds... Method and apparatus for managing write-to-read turnarounds...

2008-01-22

2008-01-22

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S154000, C711S168000

Reexamination Certificate

active

07321950

ABSTRACT:
A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

REFERENCES:
patent: 6351427 (2002-02-01), Brown
patent: 2006/0106975 (2006-05-01), Bellows et al.

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