Method and apparatus for managing snoop requests using snoop adv

Details Method and apparatus for managing snoop requests using snoop adv Method and apparatus for managing snoop requests using snoop adv

1997-10-01

1999-01-12

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711145, G06F 1208

Patent

active

058601147

ABSTRACT:
A plurality of "snoop advisory" bits are maintained by snoop management circuitry externally to the processor structure. Each snoop advisory bit corresponds to a respective "snoop advisory page" of the memory address space. Three parallel processes take place with respect to these bits. First, in response to each read access by the processor structure, if the read access is of a predetermined type (such as a cache line fill operation with intent to modify), snoop management circuitry writes a "snoop yes" value into the snoop advisory cell corresponding to the snoop advisory page which includes the address of the processor's access. Second, in response to each access by another device which shares the address space with the processor structure, a snoop request is issued to the processor structure, but only if the snoop advisory cell corresponding to the snoop advisory page which includes the address of the device's access, contains the "snoop yes" value. Otherwise, the device is allowed to perform its access directly to the memory structure without issuing a snoop request. Third, on a recurrent basis, the processor internal cache is synchronized with the memory structure and the system writes a "snoop no" value into each of the snoop advisory bits to clear them. Synchronization can involve performing a write-back on each cache line which is in a modified state, and/or invalidating each line in the cache.

REFERENCES:
patent: 5072369 (1991-12-01), Theus et al.
patent: 5325503 (1994-06-01), Stevens et al.
patent: 5404489 (1995-04-01), Woods et al.
patent: 5446863 (1995-08-01), Stevens et al.
Rhodes, Cliff, "Caches keep main memories from slowing down fast CPUs", Electronic Design, Jan. 21, 1982, U.S.A.
Strecker, William D., "Cache Memories for PDP-11 Family Computers", Computer Engineering U.S.A.
Winder, R. O. and Kaplan, K. R., "Cache-Based Computer Systems", Computer, vol. 6, No. 3, Mar. 1973, U.S.A.
IBM Microelectronics and Motorola, "PowerPC.TM. 603--RISC Microprocessor User's Manual" (1994), Chapters 5, 9 and 10.
Thorson, Mark, "Multiprocessor Cache Coherency--MOESI Model Describes Snooping Protocols", Microprocessor Report (Jun. 20, 1990), pp. 12-15.
Intel, "Pentium Processor User's Manual", vol. 1: Pentium Processor Data Book, pp. 3-20 to 3-21, 1993, United States.
Intel, "i486 Processor Hardware Reference Manual", pp. 6-1 to 6-11, 1990, United States.

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