Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Patent
1998-04-03
2000-10-17
Auve, Glenn A.
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
709251, G06F 1300
Patent
active
061346179
ABSTRACT:
A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on chip processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order. Additionally, the context managers also determine when all frames within a sequence have been received. A link control unit is provided in which loop management is provided when the host is connected to a loop. Management of the loop includes implementing mechanisms to initiate acquisition of the loop and initiate a release of the loop in response to conditions in which data is received and transmitted by the host and by other nodes on the loop.
REFERENCES:
patent: 4897834 (1990-01-01), Peterson et al.
patent: 4907224 (1990-03-01), Scoles et al.
patent: 5287463 (1994-02-01), Frame et al.
patent: 5638518 (1997-06-01), S. Malladi
patent: 5727218 (1998-03-01), Hotchkin
patent: 5826038 (1998-10-01), Nakazumi
patent: 5831679 (1998-11-01), Montgomery et al.
patent: 5948080 (1999-09-01), Baker
patent: 6014383 (2000-01-01), McCarty
patent: 6021454 (2000-02-01), Gibson
XP-002111444 QLogic Corporation, ISP2100 Intelligent Fibre Channel Processor, Data sheet; 29Jul. 1997; "Online" retrieved from the Internet url:http://qlogic.qlc.com/products/pdf/da-Authur(s) -Data Sheet.
XP-0007357779 I20 Gears Up for Embedded Use; Computer Design, vol. 36, No. 8, 1 Aug. 1997 (1997-08-1), pp. 15/16, 18. ISSN: 0010-4566 page 18, right-hand column, paragraph 2. -Author(s) -Child J.
XP-000631672 Tachyon: A Gigabit Fibre Channel Protocol Chip, Hewlett Packard Journal, vol. 47, No. 5, 1 Oct. 1996; pp. 99-112, p. 101, left-hand column, line 6-p. 111, left-hand column, line 24 -Author(s) -Smith J.A. et al.
Auve Glenn A.
LSI Logic Corporation
Ross Gary E.
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