Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
2006-01-03
2006-01-03
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
C712S214000, C712S215000
Reexamination Certificate
active
06983358
ABSTRACT:
An apparatus and method in a microprocessor having two unaligned functional unit pipelines which enables an instruction queue for the second pipeline to be placed at an intermediate pipeline stage rather than after the stage in the first pipeline that retires instructions. The apparatus maintains coherency between the status of each instruction in the queue relative to its status in the first pipeline. The status comprises an age of the instruction and a valid bit. The age specifies the stage in the first pipeline in which the instruction resides. The apparatus includes logic for updating the age and valid bit based on whether the first pipeline is stalled, on valid bits from the first pipeline, and on whether the queue is downshifting. The microprocessor selectively updates its user-visible state with the instruction execution results from the second functional unit based on the instruction age and valid bit.
REFERENCES:
patent: 5745726 (1998-04-01), Shebanow et al.
patent: 5850533 (1998-12-01), Panwar et al.
Davis E. Alan
Huffman James W.
IP-First LLC
Treat William M.
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