Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Patent
1997-01-17
1999-05-25
Gossage, Glenn
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Addressing cache memories
711146, 711212, G06F 1200
Patent
active
059078537
ABSTRACT:
A multiprocessor computer architecture containing processor caches that are kept coherent, and in particular, a duplicate cache tag subsystem and method for maintaining duplicate cache tags, are disclosed. The tag width of duplicate cache tags for a processor cache is tailored to available integrated circuit surface area, or to device pin count, without significantly sacrificing system performance. Such partial duplicate tag width may also be reduced at any time during the integrated circuit design phase, should the available integrated circuit surface area or pin-availability decrease. The method disclosed involves requesting data from memory; reading a partial duplicate cache tag list to determine if there is a partial hit; taking the data from the memory if there is no match between a requested address and the partial duplicate cache tag list; holding the data in memory or a requestor module if there is a match between the requested address and the partial duplicate cache tag list; and interrupting processor operation to confirm that the partial duplicate cache tag corresponds to an actual cache tag. The data are taken from the cache if the partial duplicate cache tag matches the actual cache tag and cache status indicates that the data have been modified. The data are taken from memory if the partial duplicate cache tag does not match the actual cache tag or cache status indicates that the data have not been modified.
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Jacobs Edward M.
Moncton Julie W.
Gossage Glenn
Hewlett--Packard Company
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