Method and apparatus for maintaining cache coherency using a sin

Details Method and apparatus for maintaining cache coherency using a sin Method and apparatus for maintaining cache coherency using a sin

1996-10-15

1999-05-11

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711117, 711118, 711133, 711141, 711144, 711145, 711146, 711215, 365 49, 364DIG1, 257676, 361760, G06F13/14;9/30

Patent

active

059039086

ABSTRACT:
A method and apparatus for controlling multiple cache memories with a single cache controller. The present invention uses a processor to control the operation of its on-chip level one (L1) cache memory and a level two (L2) cache memory. In this manner, the processor is able to send operations to be performed to the L2 cache memory, such as writing state and/or cache line status to the L2 cache memory. A dedicated bus is coupled between dice. This dedicated bus is used to send control and other signals between the processor and the L2 cache memory.

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