Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-05-12
2000-05-09
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
395281, G06F 1100
Patent
active
06061806&
ABSTRACT:
A method and apparatus for maintaining automatic termination of a bus in the event of failure of a host computer are disclosed. The method includes the steps of (a) powering a first termination control circuit and a first terminating circuit of the first bus controller with the bus; (b) generating a first control signal (1) that is of an enable state if the first bus controller is located at an end of the bus, and (2) that is of a disable state if the first bus controller is located in a middle portion of the bus; (c) coupling the first terminating circuit to the bus if the first control signal is of the enable state; and (d) decoupling the first terminating circuit from the bus if the first control signal is of the disable state.
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VLSI and Computer Peripherals, Hamburg; May 8-12, 1989; W. Proebster et al.; VLSI Based Tools for Monitoring Bus Communication Channels; pp. 4-81-84.
Caldwell Barry E.
Rowhuff Raymond S.
Thompson Kenneth J.
Beausoliel, Jr. Robert W.
Iqbal Nadeem
LSI Logic Corporation
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