Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1996-06-27
1999-05-04
Gossage, Glenn
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711148, 711147, 711141, 39520043, 39520044, 395292, 395859, 395735, G06F 1314, G06F 1324, G06F 1342
Patent
active
059000201
ABSTRACT:
A method and apparatus for maintaining processor consistency in a multiprocessor computer such as a multinode computer system are disclosed. A processor proceeds with write operations before its previous write operations complete, while processor consistency is maintained. A write operation begins with a request by the processor to invalidate copies of the data stored in other nodes. This current invalidate request is queued while acknowledging to the processor that the request is complete even though it has not actually completed. The processor proceeds to complete the write operation by changing the data. It can then execute subsequent operations, including other write operations. The queued request, however, is not transmitted to other nodes in the computer until all previous invalidate requests by the processor are complete. This ensures that the current invalidate request will not pass a previous invalidate request. The invalidate requests are added and removed from a processor's outstanding invalidate list as they arise and are completed. An invalidate request is completed by notifying the nodes in a linked list related to the current invalidate request that data shared by the node is now invalid.
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Gilbert Bruce M.
Joersz Robert T.
Lovett Thomas D.
Safranek Robert J.
Gossage Glenn
Sequent Computer Systems, Inc.
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