Method and apparatus for low power domino decoding

Details Method and apparatus for low power domino decoding Method and apparatus for low power domino decoding

2001-08-03

2003-07-15

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C326S106000, C326S107000, C326S108000

Reexamination Certificate

active

06593776

ABSTRACT:

BACKGROUND
1. Field
An embodiment of the present invention relates to the field of decoding, and, more particularly, to a low power domino decoding approach.
2. Discussion of Related Art
For microprocessors and other integrated circuits, designers continue to focus on reducing delays to provide increasingly faster integrated circuits.
Additionally, increasing power consumption of microprocessors and other integrated circuits (ICs) has become one of the major issues for current and next generation designs. Power-related costs (e.g. cooling and power delivery) can have a significant impact on the overall cost of an integrated circuit chip and, therefore, cut into profit margins in an increasingly competitive marketplace. Additionally, high power consumption and junction temperatures can limit the performance of high-end microprocessors and other ICs.


REFERENCES:
patent: 5077495 (1991-12-01), Torimaru et al.
patent: 5970018 (1999-10-01), Iwata et al.
patent: 5982702 (1999-11-01), Bosshart

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