Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-02-01
2001-09-25
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S090000, C326S095000, C326S083000, C327S391000, C327S067000
Reexamination Certificate
active
06294933
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to reducing power consumption of electric circuits, and more particularly to a low power differential signaling technique that converts single-ended signals to differential signals to reduce power consumption.
DESCRIPTION OF RELATED ART
CMOS (complementary metal oxide semiconductor) technology is generally used for low powered devices such as low power microprocessors, and microcontrollers, and also for low power computing devices including laptop or handheld computers or the like. Although CMOS technology is generally lower in power compared to other technologies such as bi-polar devices, CMOS circuits still consume a considerable amount of power during switching. At higher frequencies, the power consumption becomes significant and problematic. This is particularly true for clock circuits, which can consume 40%-50% or more power of the overall electronic circuit. CMOS circuitry is generally comprised of P channel and N channel transistors that can be configured to operate as any type of basic electronic circuit device, such as resistors and capacitors and may further be implemented as basic logic devices, such as buffers, inverters, gates, etc. CMOS logic devices generally comprise complementary P/N channel transistor pairs coupled to perform switching functions.
The average power consumption of a standard CMOS circuit is the summation of four different types of power loss, including leakage power, static power, dynamic power, and short circuit power. The leakage power is a result of leakage current through a CMOS device that is supposedly turned off. Leakage power is a characteristic of the particular CMOS technology being used and is usually negligible. The static power is the power loss that occurs when no signal is propagating through the circuitry. The static power loss can be reduced or otherwise eliminated by avoiding the use of circuits which always use current for proper biasing. The dynamic power results from current flow through parasitic capacitances of the devices along the signal traces of the circuit on a chip or printed circuit board (PCB) and is generally responsible for the largest consumption of power in the circuit. The short circuit power results when both complimentary transistors of a switch are partially on resulting in a resistive path to ground. The short circuit power occurs during switching and may be reduced with faster switch operation.
Consumers are constantly demanding greater functionality and convenience. To achieve greater functionality, the designer must pack a greater number of circuit devices into the same or smaller area and operate the circuitry at a higher frequency. A significant amount of convenience is achieved by enabling the circuitry to operate using battery power for longer periods of time. Since it is desired to also reduce the battery size, it is necessary to reduce power consumption to allow a smaller battery to be used. However, higher frequency operation results in a higher power consumption for both the dynamic and short circuit types of power loss. Circuit designers are also faced with the challenge of maintaining signal. integrity throughout the circuit. Signal integrity is degraded by parasitic capacitance on the signal traces and becomes greater with longer signal traces. To maintain signal integrity, many designers chain buffers together along signal traces to overcome the parasitic capacitance. However, such buffer chaining increases overhead circuitry and results in even greater power consumption. Down stream buffers must be relatively large to overcome large parasitic capacitances.
Many solutions have been proposed and used to reduce power consumption. Single ended circuit designs and techniques are often used to achieve a lower voltage swing relative to ground. The dynamic power is defined by the following equation:
P
dym
=C
p
V
2
f
where P
dym
is dynamic power, C
p
is parasitic capacitance, V is the voltage, and f is the frequency of operation. The power supply voltage is typically defined between V
SS
(or ground) and V
DD
. Thus, the dynamic power may be more specifically defined using the following equation:
P
dym
=C
p
V
DD
V
sig
f
where V
sig
is the voltage swing of the signal, which is typically between V
SS
and V
DD
. Therefore, the single ended techniques attempt to reduce V
sig
to thereby reduce power. Single ended techniques, however, typically require an external voltage reference or a voltage reference device which increases circuit components and often requires an external source. Furthermore, voltage references must be reasonably precise which often complicates the overall design.
Differential techniques have also been attempted to reduce power. Emitter coupled logic (ECL) and current mode logic (CML) circuitry are differential technologies used for bi-polar transistor circuits. However, bipolar transistors consume a significant amount of power and are generally not applicable to CMOS. CMOS differential techniques result in increased static power loss since current always flows through the circuit regardless of whether a signal is being propagated. Differential design effectively doubles the parasitic capacitance and thus would otherwise double the dynamic power loss at the same voltage and frequency level. However, differential signals have increased immunity to common mode noise so that the differential voltage may be concomitantly reduced by at least one-half to counteract the increased parasitic capacitance. Therefore, differential techniques attempt to reduce the voltage swing of the signal to less than half the voltage supply differential to thereby result in power savings.
One particular differential technique is known as low-voltage differential signaling (LVDS). LVDS technology requires a current reference device thereby increasing circuitry complexity. LVDS further requires an external load resistor that must be relatively precise. The current reference and load resistor result in increased cost of the overall circuit. Furthermore, LVDS is standardized at approximately 350 millivolts so that power savings are limited in standard design.
It is desired to apply low power techniques to different technologies including CDR1 (0.35 microns at V
DD
=5 volts), CDR3 (0.25 microns at V
DD
=3.3 volts) or other high performance CMOS technologies such as HIP6 (0.18 micron at V
DD
=2.0 volts) or HIP7 (0.15 micron at V
DD
=1.5 volts).
REFERENCES:
patent: 5504782 (1996-04-01), Campbell, Jr.
patent: 5694060 (1997-12-01), Brunt et al.
patent: 5949253 (1999-09-01), Bridgewater, Jr.
patent: 5977796 (1999-11-01), Gabara
patent: 5986473 (1999-11-01), Krishnamurthy et al.
patent: 6025742 (2000-02-01), Chan
patent: 6111431 (2000-08-01), Estrada
Hui Zhang et al., “Low-Swing Interconnect Interface Circuits”, University of California at Berkeley, E-mail address, hui@eecs.berkeley.edu; 6 pgs.
Chun Christopher Ky
Muh Matthew
Motorola Inc.
Tokar Michael
Tran Vibol
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