Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2006-02-21
2006-02-21
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S031000, C326S032000, C326S034000
Reexamination Certificate
active
07002367
ABSTRACT:
An apparatus is described having a feedback loop. The feedback loop has an output that approaches a steady state as a data line voltage approaches a reference voltage. The apparatus also includes a driving transistor that drives the data line. The driving transistor has an output impedance that is controlled by the feedback loop output, the feedback loop output keeps the driving transistor output impedance within a high output impedance region when the feedback loop output reaches the steady state.
REFERENCES:
patent: 5134311 (1992-07-01), Biber et al.
patent: 5185538 (1993-02-01), Kondoh et al.
patent: 5677639 (1997-10-01), Masiewicz
patent: 5687122 (1997-11-01), Merritt
patent: 5796661 (1998-08-01), Kim
patent: 5930185 (1999-07-01), Wendell
patent: 6052317 (2000-04-01), Miura
patent: 6072728 (2000-06-01), Merritt
patent: 6141257 (2000-10-01), Rochard
Fazio, Al, et al., “Intel StrataFlash Memory Technology Development and Implementation”, Inel Technology Journal Q4 1997, pp. 1-13.
Gasbarro James A.
Lau Benedict C.
Nguyen Huy M.
Vu Roxanne T.
Yu Leung
Lee & Hayes PLLC
Rambus Inc.
Tran Anh Q.
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