Computer graphics processing and selective visual display system – Computer graphics display memory system – Cache
Reexamination Certificate
1999-09-30
2003-11-25
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Cache
C345S501000, C345S537000, C345S556000
Reexamination Certificate
active
06654022
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an improved data processing system and, in particular, to a method and system for computer graphics processing system, specifically, data transfer between graphic system components.
2. Description of Related Art
Computer graphic processing is computationally expensive. Data processing systems usually contain several performance enhancements for increasing the speed at which computer graphics can be generated, but these enhancements may be accompanied by quality tradeoffs.
The efficiency of the memory utilization is one factor affecting the efficiency of computer graphic processing. Rapid advances in integrated circuit technology and in computer architecture have resulted in an increasing “memory reference delay gap” between relatively fast processing units and relatively slow memory. High performance processors with high throughput are available as commercial products. However, in order to run at their peak speeds, these high performance systems require memory systems that are able to send data to the processor as fast as the processor requires, otherwise the processor stalls while it is waiting for data to be delivered. Such memory systems may be complex and/or expensive. As a result, the performance bottleneck of many current high performance computer systems is not the speed of the processor but rather the efficiency of the memory system.
In order to overcome the problem of an increasingly large memory reference delay gap between fast processing units and slow memory, cache memories are used. Cache memory is a small, high speed memory between a processor or processors and a memory subsystem of a computer system. Its primary purpose is to provide high speed data/instruction accesses without the associated cost of an entire memory that uses high speed technology. This is achieved by keeping data and/or instructions that are expected to be referenced in the near future in the cache.
When the required data for a requested memory transaction exists in the cache, a “cache hit” is said to occur, and the required data does not need to be fetched from slower, main memory. In contrast, when the required data for a requested memory transaction does not exist in the cache, a “cache miss” is said to occur, and the required data must be fetched from slower, main memory. Cache misses are problematic because the amount of data that can be processed is limited to the speed at which data can be fetched from main memory. In general, system designers attempt to improve the cache hit ratio so that the number of cache misses are reduced and better performance can be obtained. As used herein, the term “cache hit ratio” is defined as the probability that a data item requested by a processor unit will be found in the cache, and the “cache miss penalty” is defined as the time that the processing unit is required to wait for the requested data item to arrive when a cache miss occurs.
The prior art teaches a technique known as prefetching in which data items are brought into the cache memory before they are actually needed. If the prefetching correctly anticipates the memory reference behavior of a program, then memory reference delay times can be overlapped with program execution—at least partially overlapped and preferably completely overlapped. The number of cache misses can then be reduced, and the performance of the program is increased.
Data reference behavior is often considered generally random, and most prior art techniques teach a simple prefetch of data items consecutively in front of or behind a current memory reference. With this type of cache behavior, cache space may be wasted to store prefetched, non-referenced data, and data items in the cache that are going to be referenced shortly might be replaced by non-referenced data.
Therefore, it would be advantageous to provide more efficient graphics memory operations so that a graphics processor does not stall while waiting for data retrieval, thereby increasing the performance of the graphics processor.
SUMMARY OF THE INVENTION
A method and apparatus for generation of pixel lookahead information in a cached computer graphics system is provided. For each pixel-based memory operation, several data items may be generated, such as numerical values representing a coordinate point in an image coordinate space or display coordinate space and characteristic data representing a color value or depth value for the pixel. In addition, lookahead data correlated with the coordinate data is generated. The pixel operation is then issued with the characteristic data, the coordinate data, and the lookahead data. The lookahead data may contain a lookahead vector, which specifies a lookahead vector direction and a lookahead vector length, and a lookahead valid flag, which indicates whether associated lookahead data is valid for the pixel operation. The lookahead direction may be computed based on the coordinate data of the pixel operation and coordinate data for a pixel operation to be performed within a threshold number of pixels operations from the pixel operation. By providing lookahead information based on the rendering state of the graphics subsystem, pixel operation intentions may be indicated prior to the issuance of a pixel operation so that the pixel data may be prefetched into a cache.
REFERENCES:
patent: 5136664 (1992-08-01), Bersack et al.
patent: 5694568 (1997-12-01), Harrison, III et al.
patent: 6084599 (2000-07-01), Nakatsuka et al.
Bella Matthew C.
McBurney Mark E.
Singh Dalip K.
Yociss Lisa L.B.
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