Method and apparatus for logically expanding the width of...

Details Method and apparatus for logically expanding the width of... Method and apparatus for logically expanding the width of...

2005-01-04

2005-01-04

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S201000, C711S171000

Reexamination Certificate

active

06839825

ABSTRACT:
A method and apparatus for minimizing memory required for storing non-binary width data structures is disclosed. The non-binary width data structure is segmented into plural segments. The segments are stored in a plurality of memory blocks. Mapper logic maps a logical address to a physical address in the memory blocks to access non-binary width entries in the non-binary width data structure stored in the memory blocks.

REFERENCES:
patent: 5479401 (1995-12-01), Bitz et al.
patent: 5680161 (1997-10-01), Lehman et al.
patent: 5857196 (1999-01-01), Angle et al.
patent: WO 9914906 (1999-03-01), None
Degermark Mikael et al., “Small Forwarding Tables for Fast Routing Lookups”, Department of Computer Science and Electrical Engineering, Luleå University of Technology, Sweden,SigComm '97 Cannes, Francepp. 3-14 (1997).

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