Method and apparatus for logic synthesis employing size independ

Details Method and apparatus for logic synthesis employing size independ Method and apparatus for logic synthesis employing size independ

1998-04-28

2000-12-26

Teska, Kevin J.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

716 5, G06F 1750

Patent

active

061675571

ABSTRACT:
Size independent timing optimization is performed on an initial circuit design using gain based models for logic cell types. A component library containing various logic elements in a plurality of sizes is provided and a single gain based model for each logic element (cell type) is created therefrom. Initial conditions for gain and delay are then established for each cell type. Gain based optimization, which is size independent, is then performed on the initial circuit design. The optimized size independent solution is then transformed into a realizable discrete circuit solution.

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"Global Wires Harmful?", R.H. Otten, 1998.

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