Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling
Reexamination Certificate
2006-11-28
2006-11-28
An, Meng-Al T. (Department: 2195)
Electrical computers and digital processing systems: virtual mac
Task management or control
Process scheduling
C718S100000, C718S102000, C710S200000
Reexamination Certificate
active
07143414
ABSTRACT:
Processor threads in a multi-processor system can concurrently lock multiple semaphores by providing a lock command which includes the semaphore value and a semaphore number. Each processor is allocated two or more addressable semaphore stores, each of which include a multi-bit field identifying the requested semaphore and a one bit field identifying the locked status of the requested semaphore. The semaphore number determines which of the allocated semaphore stores are to be used for processing the lock command.
REFERENCES:
patent: 4805106 (1989-02-01), Pfeifer
patent: 4907228 (1990-03-01), Bruckert et al.
patent: 5142632 (1992-08-01), Tychon et al.
patent: 5159686 (1992-10-01), Chastain et al.
patent: 5233701 (1993-08-01), Nakata
patent: 5261106 (1993-11-01), Lentz et al.
patent: 5276886 (1994-01-01), Dror
patent: 5339443 (1994-08-01), Lockwood
patent: 5485593 (1996-01-01), Baker
patent: 5548780 (1996-08-01), Krein
patent: 5613139 (1997-03-01), Brady
patent: 5664092 (1997-09-01), Waites
patent: 5675829 (1997-10-01), Oskouy et al.
patent: 5696939 (1997-12-01), Iacobovici et al.
patent: 5734909 (1998-03-01), Bennett
patent: 5842018 (1998-11-01), Atkinson et al.
patent: 5852731 (1998-12-01), Wang et al.
patent: 5862180 (1999-01-01), Heinz
patent: 5864653 (1999-01-01), Tavallaei et al.
patent: 5893157 (1999-04-01), Greenspan et al.
patent: 5901308 (1999-05-01), Cohn et al.
patent: 5931923 (1999-08-01), Roberts
patent: 6018785 (2000-01-01), Wenniger
patent: 6026427 (2000-02-01), Nishihara et al.
patent: 6029190 (2000-02-01), Oliver
patent: 6070254 (2000-05-01), Pratt et al.
patent: 6079013 (2000-06-01), Webb et al.
patent: 6105085 (2000-08-01), Farley
patent: 6119246 (2000-09-01), McLaughlin et al.
patent: 6122713 (2000-09-01), Huang et al.
patent: 6125401 (2000-09-01), Huras et al.
patent: 6128706 (2000-10-01), Bryg et al.
patent: 6131094 (2000-10-01), Gord
patent: 6134579 (2000-10-01), Tavallaei et al.
patent: 6134619 (2000-10-01), Futral et al.
patent: 6154847 (2000-11-01), Schofield et al.
patent: 6161169 (2000-12-01), Cheng
patent: 6173313 (2001-01-01), Klots et al.
patent: 6182108 (2001-01-01), Williams et al.
patent: 6199094 (2001-03-01), Presler-Marshall
patent: 6725457 (2004-04-01), Priem et al.
patent: 6748470 (2004-06-01), Goldick
patent: 7036125 (2006-04-01), Basso et al.
patent: 7062583 (2006-06-01), Kolinummi et al.
patent: 7089555 (2006-08-01), Calvignac et al.
patent: 7100161 (2006-08-01), Latour
patent: 2002/0138544 (2002-09-01), Long
patent: 2003/0002440 (2003-01-01), Calvignac et al.
patent: 2003/0005195 (2003-01-01), Davis et al.
patent: 2003/0060898 (2003-03-01), Jenkins et al.
patent: 2003/0115476 (2003-06-01), McKee
patent: 2003/0145035 (2003-07-01), de Bonet
patent: 0953903 (1999-11-01), None
patent: 1033654 (2000-09-01), None
patent: 4361340 (1992-12-01), None
patent: 8329019 (1996-12-01), None
patent: 9044376 (1997-02-01), None
patent: 1 1039176 (1999-02-01), None
patent: 9231123 (1999-02-01), None
patent: 11272480 (1999-10-01), None
patent: 2001005694 (2001-01-01), None
patent: 2001022720 (2001-01-01), None
patent: WO9603697 (1996-02-01), None
Focazio et al., “Microkernel Synchronization Primitives”, IBM Technical Disclosure Bulletin, 1995, pp. 283-289.
Focazio et al., “Microkernel Semaphores”, IBM Technical Disclosure Bulletin, 1995, pp. 111-117.
IBM Technical Disclosure Bulletin vol. 30, No. 3, Aug. 1987, p. 1203, “Non-Atomic (Ordered) Semaphore Operations”.
Research Disclosure, Aug. 2000, p. 1442, article 436131, “User lever writing to a pinned kernel buffer in an SMP system”.
IBM Technical Disclosure Bulletin vol. 37, No. 12, Dec. 1994, “Error Handler Installation Procedure”, pp. 239-240.
IBM Technical Disclosure Bulletin vol. 37, No. 06A, Jun. 1994, “Shared Memory Cluster—A Scalable Multiprocessor Design”, pp. 503-507.
IBM Technical Disclosure Bulletin vol. 30, No. 5, Oct. 1987, “Fast Method for Simultaneous Exclusive Table Modifications”, pp. 348-350.
IBM Technical Disclosure Bulletin vol. 38 No. 4, Apr. 1995, “Hardware Contention Serialization Algorithm”, pp. 73-77.
IBM Technical Disclosure Bulletin vol. 33, No. 4, Sep. 1990, “Store Purge Pipeline for Mid-Range Processor”, pp. 299-301.
IBM Technical Disclosure Bulletin vol. 36, No. 6A, Jun. 1993, “Emulator DosExit Processing for Reporting Errors”, pp. 255-256.
Research Disclosure No. 317, Sep. 1990, “Improved Error Detection Using MP Fields”.
IBM Technical Disclosure Bulletin No. 9. Feb. 1991, “System Support for Multiprocessing Without an Atomic Storage”, pp. 18-23.
E. Chang, “N-Philosophers: an Exercise in Distributed Control”, Computer Networks vol. 4, No. 2,, Apr. 1980, pp. 71-76.
P. Bohannon et al., “Recoverable User-Level Mutual Exclusion”, Proceedings, 7thIEEE Symposium on Parallel and Distributed Processing (Cat. No. 95TB8131), 1995, pp. 293-301.
J. Thornley et al., “Monotonic counters: a New Mechanism for Thread Synchronization”, Proceedings 14thInternational Parallel and Distributed Processing Symposium, IPDPS 2000, pp. 573-582.
K. C. Tai et al., “VP: A New Operation for Semaphores”, Operating Systems Review, vol. 30, No. 3, Jul. 1996, pp. 5-11.
Mei Chen Chia et al., “A Resource Synchronization Protocol for Multiprocessor Real-Time Systems”, Proceedings of the 1994 International Conference on Parallel Processing, Pt. vol. 3, 1994, pp. 159-162.
Heng Liao et al., “Hardware Support for Process Synchronization Algorithms”, Mini-Micro Systems, vol. 16, No. 9, Sep. 1995, pp. 7-13.
Chung Wu Chaio et al., “The Design and Implementation of a Distributed Semaphore Facility: DISEM”, Proceedings of the National Science Council, Republic of China, Part A, vol. 19, No. 4, Jul. 1995, pp. 319-320.
D. Scholefield, “Proving Properties of Real-Time Semaphores”, Science of Computer Programming, vol. 24, No. 2, Apr. 1995, pp. 159-181.
D. Weiss, “Shared Bus Semaphore Detector Proposal”, Motorola Technical Developments, vol. 3, Mar. 1983, pp. 74-78.
J. Milde et al., “Realization of Synchronization Tools and their Efficiency in the Multiprocessor System M5PS”, 10thIMACS World Congress on System Simulation and Scientific Computation, vol. 1, 1982, pp. 333-335.
N. Wait, “VME- a Microcomputer Bus on Europe”, New Electronics vol. 15, No. 16,Aug. 17, 1992, pp. 57-58.
N. Marovac, “Interprocess Syncrhonization and Communication in Distributed Architectures”, 3rdInternaTional Conf. On Computer Science) Chile, 1983 pp. 1-16.
N. Marovac, “On Interprocess Interaction in Distributed Architectures”, Computer Architecture News vol. 11, No. 4, Sep. 1983, pp. 17-22.
T. Balph, “Interprocessor Communication in a Tightly coupled Multiple Processor Architecture”, Second Annual Phoenix Conference on Computers and Communications, 1983 Conf. Proceedings pp. 21-25.
Heddes Marco
Jenkins Steven Kenneth
Leavens Ross Boyd
Likovich, Jr. Robert Brian
An Meng-Al T.
Cockburn Josh G.
Dillon & Yudell LLP
To Jennifer N.
LandOfFree
Method and apparatus for locking multiple semaphores does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for locking multiple semaphores, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for locking multiple semaphores will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3642444