Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1998-09-09
2001-04-24
Nguyen, Than (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S150000, C711S152000, C711S164000, C711S165000, C711S206000, C711S207000
Reexamination Certificate
active
06223263
ABSTRACT:
The present invention relates to computer systems and more particularly to a replacement algorithm for data stored in a memory region in which the data is locked or unlocked.
BACKGROUND
Computer systems, from small handheld electronic devices to medium-sized mobile and desktop systems to large servers and workstations, are becoming increasingly pervasive in our society. Computer systems typically include one or more processors. A processor manipulates and controls the flow of data in a computer. Increasing the speed of the processor tends to increase the computational power of the computer, and processor designers employ many different techniques to increase processor speed to create more powerful computers for consumers. One such technique is to provide circuitry that supports tickle instructions.
A tickle instruction is placed in a sequence of instructions prior to a data access instruction. The tickle instruction checks processor resources to determine if the data access instruction will cause a fault (or exception) to occur, and if so, to eliminate the fault. The tickle instruction eliminates a fault by causing the fault to occur early, forcing the processor to launch the appropriate exception handler to remedy the fault. While the fault is being remedied, the processor may execute other instructions in the instruction sequence. Ideally, by the time the processor executes the data access instruction, th e fault has been eliminated, so the processor does not need to stall the execution of subsequent instructions while remedying the fault. Thus processor speed is improved.
For example, one type of tickle instruction is a faulting probe instruction. A faulting probe instruction is inserted into an instruction sequence before an associated load or store instruction. Upon executing the faulting probe instruction, the processor performs a fault check lookup of the data needed to perform a faultless execution of the subsequent load or store instruction. For example, the processor verifies that the proper address translation data is stored in the translation buffer and that the processor has the necessary privileges to access the data. If no faults are detected, execution of the instruction sequence proceeds normally. If a fault is detected, the appropriate exception handler is launched to either load the needed translation data into the translation buffer or to get privileges to access the data. The load or store instruction may then be executed without causing a fault or exception.
Note that there are other tickle instructions that perform similar functions, such as faulting prefetch instructions.
Unfortunately, there are problems associated with this usage of tickle instructions. Instructions executed between the tickle instruction and its associated data access instruction may modify the state of the processor. In some cases, this modification may result in a fault upon execution of the data access instruction, notwithstanding the fact that the associated tickle instruction was previously executed. For example, in the scenario presented above, suppose new data is loaded into the translation buffer after the faulting probe instruction is executed but before the load or store instruction is executed. Depending on the size of the translation buffer and the replacement algorithm used, the new data may replace the data needed by the load or store instruction. If so, a fault occurs upon executing the load or store instruction.
At best, this fault may result in a delay while the processor re-loads the necessary data into the translation buffer, thereby reducing processor speed. In some cases, however, the fault may result in an error, thereby halting program execution or corrupting data integrity.
SUMMARY OF THE INVENTION
A method and apparatus is described for managing a memory region that stores locked and unlocked data. When data stored in the memory region is accessed, the associated index of that data is stored in a locked index queue. While the index is stored in the locked index queue, the data is locked.
Other features and advantages of the present invention will be apparent from the accompanying drawings and the detailed description that follows.
REFERENCES:
patent: 5175837 (1992-12-01), Arnold et al.
patent: 5285528 (1994-02-01), Hart
patent: 5341491 (1994-08-01), Ramanujan
patent: 5983329 (1999-11-01), Thaler et al.
Mathews Gregory Scott
Yuen Selina Sze Wan
Intel Corporation
Kaplan David J.
Nguyen Than
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