Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2002-01-28
2004-02-10
Cho, James H (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S037000, C327S261000
Reexamination Certificate
active
06690201
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to locating data transition regions, and more particularly to using located data transition regions in a programmable logic device to improve performance.
BACKGROUND OF THE INVENTION
Programmable logic devices exist as a well-known type of integrated circuit that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic devices, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBS, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBS, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
Even though FPGAs are very flexible and can be used to implement many circuits, they have some performance limitations, such as longer signal delays and lower gate counts. These limitations hinder use of FPGAs on high-speed applications, namely, those applications with real-time processing of information.
For example, communication circuits move data at rates of speed in excess of 622 million bits per second (Mbps). Reliable serial data sampling at speeds over 622 Mbps is difficult in part due to clock and data jitter and skew, as well as data-to-data skew on a wide bus (8 or more bits wide) and inter-symbol interference. Conventionally, all channels have been sampled synchronously. For example, in a source synchronous application, data is provided in parallel with a respective clock signal. Though this forwarded clock signal will not be exactly in-phase and in-frequency with the internally generated sampling clock derived from the forwarded clock via a DCM/PLL/DLL with inherent increase in sampling jitter. Accordingly, this makes it difficult to process data in parallel due to misalignment of data bits. Moreover, higher data rates continue to narrow the data-sampling window. Alternatively, asynchronous data sampling may be used. However, asynchronous data sampling still needs to be reliable to associate data to a non-transition area, and asynchronous data sampling operates at speeds proximal or equal to the data rate.
For these high-speed applications, application specific integrated circuits (ASICs) or application specific standard products (ASSPs) have conventionally been used. Unfortunately, communication circuits implemented as ASICs or ASSPs have several disadvantages. One such disadvantage is the time-to-market risks associated with the relatively long cycle time necessary for the implementation of a new ASIC design. An additional disadvantage of using ASICs for communication circuits is that ASICs are “hardwired” and thus conventionally are not reconfigurable for a new application or application upgrade.
Accordingly, it would be desirable and useful to provide a programmable logic device that was capable of handling such high-speed data rates. Moreover, it would be desirable and useful to provide such a solution that would work in a synchronous or asynchronous context, whether in a programmable logic device or other integrated circuit, including, but not limited to, ASICs and ASSPs.
SUMMARY OF THE INVENTION
An aspect of the present invention is a data sampling circuit. More particularly, a delay line is provided along with a plurality of tap circuits coupled to the delay line. The plurality of tap circuits is coupled at locations for progressively delaying an input data signal. A tap circuit of the plurality of tap circuits comprises a sampling device and a metastable recovery device. The sampling device and the metastable recovery device are coupled in series and configured to receive, sample and stabilize the input data signal progressively delayed. Accordingly, outputs from the plurality of tap circuits provide at least a portion of a vector indicative of a transition region of the input data signal.
An aspect of the present invention is a hybrid data sampling circuit. More particularly, a first delay line is provided having a series of gates and having a first plurality of nodes interspersed between the gates. The first plurality of nodes is located for tapping a progressively delayed input signal with a first granularity. A plurality of second delay lines is coupled to the first plurality of nodes. The plurality of second delay lines has a second plurality of nodes located for tapping the progressively delayed input signal with a second granularity. A plurality of tap circuits is coupled to the second plurality of nodes. The plurality of tap circuits includes a sampling device and a metastable recovery device, where the sampling device and the metastable recovery device are coupled in series and configured to receive, sample and stabilize the progressively delayed input signal. Accordingly, outputs from the plurality of tap circuits provide at least a portion of a vector indicative of a transition region of the input data signal.
An aspect of the present invention is a method for determining a transition region of an input signal. More particularly, the input signal is progressively delayed. The input signal progressively delayed is tapped at a plurality of locations to provide a plurality of progressively delayed versions of the input signal. The plurality of progressively delayed version of the input signal is sampled to provide at least a portion of a vector indicative of the transition region of the input signal.
An aspect of the present invention is a method for determining a transition region of an input signal. More particularly, the input signal is progressively delayed. The input signal progressively delayed is tapped at a first plurality of locations to provide a first plurality of progressively delayed versions of the input signal of a first granularity. The first plurality of progressively delayed versions of the input signal of the first granularity is progressively delayed to provide a second plurality of progressively delayed versions of the input signal of a second granularity. The second plurality of progressively delayed versions of the input signal of the second granularity is tapped at a second plurality of locations. The second plurality of progressively delayed version of the input signal of the second granularity is sampled to provide at least a portion of a vector indicative of the transition region of the input signal.
An aspect of the present invention is a method for timing signal data recovery. More particularly, falling data samples and rising data samples are obtained, and the falling data samples are moved to a domain of the rising data samples. The falling data samples and the rising data samples are processed in sequential pairs, and data transition region information is determined from the sequential pairs. The data transition region information is provided to a state machine and processed with the state machine to obtain output therefrom.
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Baetoniu Catalin
Sawyer Nicholas J.
Simkins James M.
Webostad W. Eric
Xilinx , Inc.
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