Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2004-12-06
2008-03-04
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07340711
ABSTRACT:
Some embodiments of the invention provide a method for defining routes in a design layout. The method defines at least one particular wiring layer that has at least two regions with different local preferred wiring directions. The method then uses the differing local preferred wiring directions to define a detailed route on the wiring layer. In some embodiments, the method defines a first route that traverse first and second regions between two layers by using a first via that has a first pad in the second region. The method also defines a second route that traverses the second region and a third region in the two layers by using a second via that has a second pad in the second region, where the first and second pads have different shapes.
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Cherukuri Deepak
Hetzel Asmus
Jacques Etienne
Cadence Design Systems Inc.
Garbowski Leigh M.
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