Electricity: measuring and testing – Impedance – admittance or other quantities representative of...
Reexamination Certificate
2001-06-29
2003-04-29
Le, N. (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
C327S513000
Reexamination Certificate
active
06556022
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of compensation circuits and, more particularly, to a method and apparatus to compensate for local process, voltage, and temperature variations.
BACKGROUND OF THE RELATED ART
In some precision circuit operations, process, voltage and temperature (PVT) variations can affect circuit performance, such as timing skew. For example, on a semiconductor die, deviations in a fabrication process and/or variations in circuit operation may result in PVT variations of varying quantity across the die. These variations then could produce local variations in circuit performance.
In an attempt to provide PVT compensation, a PVT sensing technique could use a PVT sensor to obtain an average PVT information for the die. For example, a global PVT sensor can route a detection path around the die and obtain the average environment condition. However, this technique fails to separately sense and compare the local variations. Global compensation techniques do not differentiate among the local sensed regions.
As an example, a circuit employing a phase lock loop (PLL) will consume substantially more power and generate more heat than a less active circuit. Thus, a region of the die at the PPL site will have a higher local temperature than some other region of the die and this temperature difference can result in a temperature gradient. A global temperature sensing technique would fail to localize this hotter location, since it would ascertain the average parameter. If a global PVT sensor is used, PVT compensation would be based on a global average and a true indication of the region about the PLL circuit would not be readily available. In application, a distributed clock signal which is typically buffered at various localized buffer locations, may deviate more than the allowable tolerance at a given buffer location due to the PVT variation at that location. The PVT differential at two given locations may be sufficient to introduce unacceptable timing skew between the two locations. A localized PVT compensation technique would allow for PVT compensation to be achieved at the local level.
REFERENCES:
patent: 5087829 (1992-02-01), Ishibashi et al.
patent: 5166559 (1992-11-01), Ishihara
patent: 5691703 (1997-11-01), Roby et al.
patent: 5880612 (1999-03-01), Kim
patent: 5889431 (1999-03-01), Csanky
patent: 5917356 (1999-06-01), Casal et al.
patent: 6025792 (2000-02-01), Smith
patent: 6144218 (2000-11-01), Smith et al.
patent: 6150862 (2000-11-01), Vikinski
patent: 6177788 (2001-01-01), Narendra et al.
patent: 6292016 (2001-09-01), Jefferson et al.
patent: 6324084 (2001-11-01), Fujisawa
Hsu Jen-Tai
To Thomas
Volk Andrew M.
Blakley Sokoloff Taylor & Zafman LLP
Intel Corporation
Le N.
LeRoux Etienne P
LandOfFree
Method and apparatus for local parameter variation compensation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for local parameter variation compensation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for local parameter variation compensation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3088351