Method and apparatus for loading an instruction buffer of a proc

Details Method and apparatus for loading an instruction buffer of a proc Method and apparatus for loading an instruction buffer of a proc

1998-02-09

2000-05-16

Donaghue, Larry D.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Scoreboarding, reservation station, or aliasing

712215, 712208, 711214, G06F 930

Patent

active

060651105

ABSTRACT:
A method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue are disclosed. The processor capable of out-of-order instruction issue includes an instruction cache having multiple cache lines. The instruction cache is coupled to an instruction buffer via a multiplexor. The instruction buffer includes several slots, and these slots are sequentially filled by instructions from the instruction cache under the supervision of the multiplexor. The slot in which the first instruction resides is dictated by a fetch address. Any empty slot in the instruction buffer will be filled with instructions from a subsequent cache line of the instruction cache if the first instruction does not reside in the first slot of the instruction buffer.

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