Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2002-05-28
2004-11-23
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S156000, C711S005000, C709S241000, C709S241000
Reexamination Certificate
active
06823432
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The invention relates generally to buffering of data in a multi-bank memory and more particularly to a method and apparatus for buffering data cells in a multi-bank memory within a communication switch.
BACKGROUND OF THE INVENTION
A communication network is used to transport data between various parties connected to the network. Cell-based and packet-based networks typically include a number of switches that can receive data from a number of different sources and deliver it to a number of different destinations. These switches are intercoupled such that data can be transmitted throughout the network. In order to allow data to be received from a plurality of sources and delivered to a plurality of different outputs, buffering capabilities are typically included within these switches.
The output buffer of a typical packet- or cell-based switch includes buffering memory that stores received data cells or packets prior to delivering the cells or packets to the various outputs of the switch. In many cases, the buffering memory utilized within these output buffers includes a number of banks. The interaction between the various banks in the memory can place some constraints on the types of memory operations that can be executed. For example, if a bank is read from during a memory cycle, it cannot be written to during the same cycle. Various memory constraints can exist within different memory systems.
In order to maximize the usage of the buffering memory, it is important to ensure that if there is remaining space in the buffering memory, it can be utilized for write operations. This may be difficult if a number of the memory banks have been filled, and read operations are directed towards the unfilled banks. When this scenario occurs, the write operations are unable to access the banks that are not filled due to the fact that the read operations are being performed. Typically, the read operations, which dequeue data cells or packets from the buffering structure for output are controlled external to the circuitry performing the actual buffering. As such, the control of which data is dequeued is outside of the memory management circuitry.
Therefore, a need exists for a method and apparatus that allows for maximum usage of multi-bank buffering memory such that when space is available within the buffering memory, it can be accessed even though memory operations are constrained based on fixed dequeuing operations.
REFERENCES:
patent: 4590586 (1986-05-01), Zenk et al.
patent: 5432920 (1995-07-01), Yazawa et al.
patent: 6415366 (2002-07-01), Chen et al.
Chen Jason Chung-Shih
Heller Albert D.
Ruffle Paul M.
Anderson Matthew D.
Kim Matthew
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