Method and apparatus for limiting the slew rate of output driver

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction

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Details

326 50, 326 87, 327170, H03K 190948

Patent

active

057034966

ABSTRACT:
The output driver includes a plurality of transistor devices connected to an output line. In one arrangement, a separate flash-programmable element is connected to each of the plurality of transistor devices. Each of the separate flash elements receives the data signal along an input line and outputs the data signal if the flash cell is enabled (or not programmed) and outputs a constant voltage level, regardless of the data signal, if the flash element is not enabled. Hence, only those output transistors connected to flash elements that have been enabled are triggered by the output signal. Other transistors merely receive a constant voltage and are, therefore, not triggered regardless of the output signal. In another arrangement, the output driver is configured to forward output signals to all of the output transistors but the flash cells are programmed to adjust a time delay occurring prior to reception by the output transistors. This is achieved by setting the threshold voltage for the flash elements to differing values. The flash cells may be programmed to provide sequentially increasing time delays. Hence, the corresponding output transistors are activated sequentially resulting in a reduction in the increase of current drawn as a function of time, thereby reducing the total amount of voltage noise. In either arrangement, the various flash-programmable elements of the output drivers of the integrated circuit chip are programmed after fabrication of the chip.

REFERENCES:
patent: 4959564 (1990-09-01), Steele
patent: 5039874 (1991-08-01), Anderson
patent: 5194765 (1993-03-01), Dunlop et al.
patent: 5387824 (1995-02-01), Michelsen
patent: 5489858 (1996-02-01), Pierce et al.
patent: 5638007 (1997-06-01), Sabin

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